[uvm] 寄存器模型reg_rm read/write

寄存器模型需要有走配置reg专门通道的agent， 实战中是bus_agent; 有相关的bus_driver/monitor/sqr;
通过adapter把数据给到bus_itme/tranaction；
item就是uvm实战的bus_tranaction 或者pcie_item等等 ;
adapter 产生的pcie_item可以直接给sqr/driver

class case0_cfg_vseq extends uvm_sequence;
//在sequence中使用
   `uvm_object_utils(case0_cfg_vseq)
   `uvm_declare_p_sequencer(my_vsqr)
   
   function  new(string name= "case0_cfg_vseq");
      super.new(name);
   endfunction 
   
   virtual task read_reg(input bit[15:0] addr, output bit[15:0] value);
      uvm_status_e   status;
      uvm_reg target;
      uvm_reg_data_t data;
      uvm_reg_addr_t addrs[];
      target = p_sequencer.p_rm.default_map.get_reg_by_offset(addr);
      if(target == null) 
         `uvm_error("case0_cfg_vseq", $sformatf("can't find reg in register model with address: 'h%0h", addr))
      target.read(status, data, UVM_FRONTDOOR);
      void'(target.get_addresses(null,addrs));
      if(addrs.size() == 1)
         value = data[15:0]; 
      else begin
         int index;
         for(int i = 0; i < addrs.size(); i++) begin