axi vip tb code

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最新推荐文章于 2024-01-29 11:01:58 发布

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本文链接：https://blog.csdn.net/weixin_39060517/article/details/132596565

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`timescale 1ns / 1ps

import axi_vip_pkg::*;
import axi_vip_design_axi_vip_0_0_pkg::*;

module tb_axi_vip();

    /*************************************************************************************************
    * 信号声明
    *************************************************************************************************/
    logic                   aclk;
    logic                   aresetn;
    logic  [31:0]           gpio_i;
    logic  [31:0]           gpio_o;

    //used in API and parital randomization for transaction generation and data read back from driver
    axi_transaction                         wr_transaction;                // Write transaction
    axi_transaction                         rd_transaction;                // Read transaction

    xil_axi_uint                            mtestID;                       // ID value for WRITE/READ_BURST transaction
    xil_axi_ulong                           mtestADDR;                     // ADDR value for WRITE/READ_BURST transaction
    xil_axi_len_t                           mtestBurstLength;              // Burst Length value for WRITE/READ_BURST transaction
    xil_axi_size_t                          mtestDataSize;                 // SIZE value for WRITE/READ_BURST transaction
    xil_axi_burst_t                         mtestBurstType;                // Burst Type value for WRITE/READ_BURST transaction
    xil_axi_lock_t                          mtestLOCK;                     // LOCK value for WRITE/READ_BURST transaction
    xil_axi_cache_t                         mtestCacheType = 3;            // Cache Type value for WRITE/READ_BURST transaction
    xil_axi_prot_t                          mtestProtectionType = 3'b000;  // Protection Type value for WRITE/READ_BURST transaction
    xil_axi_region_t                        mtestRegion = 4'b000;          // Region value for WRITE/READ_BURST transaction
    xil_axi_qos_t                           mtestQOS = 4'b000;             // QOS value for WRITE/READ_BURST transaction
    xil_axi_data_beat                       dbeat;                         // Data beat value for WRITE/READ_BURST transaction
    xil_axi_user_beat                       usrbeat;                       // User beat value for WRITE/READ_BURST transaction
    xil_axi_data_beat [255:0]               mtestWUSER;                    // Wuser value for WRITE/READ_BURST transaction
    xil_axi_data_beat                       mtestAWUSER = 'h0;             // Awuser value for WRITE/READ_BURST transaction
    xil_axi_data_beat                       mtestARUSER = 0;               // Aruser value for WRITE/READ_BURST transaction
    xil_axi_data_beat [255:0]               mtestRUSER;                    // Ruser value for WRITE/READ_BURST transaction
    xil_axi_uint                            mtestBUSER = 0;                // Buser value for WRITE/READ_BURST transaction
    xil_axi_resp_t                          mtestBresp;                    // Bresp value for WRITE/READ_BURST transaction
    xil_axi_resp_t[255:0]                   mtestRresp;                    // Rresp value for WRITE/READ_BURST transaction

    // No burst for AXI4LITE and maximum data bits is 64
    // Write Data Value for WRITE_BURST transaction
    // Read Data Value for READ_BURST transaction
    bit [63:0]                             mtestWData;                     // Write Data
    bit[8*4096-1:0]                        Wdatablock;                     // Write data block
    xil_axi_data_beat                      Wdatabeat[];                    // Write data beats

    bit [63:0]                             mtestRData;                     // Read Data
    bit[8*4096-1:0]                        Rdatablock;                     // Read data block
    xil_axi_data_beat                      Rdatabeat[];                    // Read data beats


    /*************************************************************************************************
    * UUT
    *************************************************************************************************/
    axi_vip_design UUT (
        .aclk           ( aclk    ),
        .aresetn        ( aresetn ),
        .gpio_i         ( gpio_i  ),
        .gpio_o         ( gpio_o  )
    );
    
    localparam PERIOD = 10.0;
    initial begin
        aclk = 0;
        #(PERIOD/2);
        forever #(PERIOD/2) aclk = ~aclk;
    end

    initial begin
        gpio_i = 32'hABCD1234;
        aresetn = 0;
        #100;
        aresetn = 1; 
    end
    
    /*************************************************************************************************
    * <component_name>_mst_t for master agent
    *************************************************************************************************/
    axi_vip_design_axi_vip_0_0_mst_t                              mst_agent;
    
    initial begin
        /***********************************************************************************************
        * Before agent is newed, user has to run simulation with an empty testbench to find the hierarchy
        * path of the AXI VIP's instance.
        ***********************************************************************************************/
        mst_agent = new("master vip agent",UUT.axi_vip_0.inst.IF);  //可以先注释掉这句,打开simulator,查看路径
        mst_agent.set_agent_tag("Master VIP");                      //set tag for agents for easy debug
        mst_agent.start_master();                                   // agent start to run

        mtestID             = 0;
        mtestBurstLength    = 0;
        mtestDataSize       = xil_axi_size_t'(xil_clog2(32/8));
        mtestBurstType      = XIL_AXI_BURST_TYPE_INCR;
        mtestLOCK           = XIL_AXI_ALOCK_NOLOCK;
        mtestCacheType      = 3;
        mtestProtectionType = 0;
        mtestRegion         = 0;
        mtestQOS            = 0;
        for(int i = 0; i < 256;i++) begin
            mtestWUSER = 'h0;
        end

        #200;
        @(posedge aclk);
        mtestADDR   = 0;
        mtestWData  = {32'h0,32'h1234};
        mst_agent.AXI4LITE_WRITE_BURST(
          mtestADDR,
          mtestProtectionType,
          mtestWData,
          mtestBresp
        );
        
        mtestADDR   = 0;
        mst_agent.AXI4LITE_READ_BURST(
          mtestADDR,
          mtestProtectionType,
          mtestRData,
          mtestRresp
        );       
        
    end
endmodule
/*
————————————————
版权声明：本文为CSDN博主「山音水月」的原创文章，遵循CC 4.0 BY-SA版权协议，转载请附上原文出处链接及本声明。
原文链接：https://blog.csdn.net/linbian1168/article/details/123770641
*/



   wr_transaction = master_agent.wr_driver.create_transaction("write transaction");
	wr_transaction.set_write_cmd(mtestADDR,mtestBurstType,mtestID,mtestBurstLength,mtestDataSize);
	for(int beat=0; beat<wr_transaction.get_len()+1; beat++) begin
		wr_transaction.set_data_beat(beat, beat);
		compare_data_in[beat] = beat;
	end
	wr_transaction.set_driver_return_item_policy (XIL_AXI_WLAST_RETURN);
	master_agent.wr_driver.send(wr_transaction);
	master_agent.wr_driver.wait_rsp(wr_transaction);
	
	
wr_transaction = mst_agent.wr_driver.create_transaction("write transaction");
wr_transaction.set_write_cmd(mtestADDR,mtestBurstType,mtestID,mtestBurstLeng
th,mtestDataSize); 
wr_transaction.set_data_block(mtestWData);
for(int beat=0; beat<wr_transaction.get_len()+1; beat++) begin
 wr_transaction.set_data_beat(beat, dbeat);
end
mst_agent.wr_driver.send(wr_transaction);
//-------------------------------------

rd_transaction = mst_agent.rd_driver.create_transaction("read transaction");
rd_transaction.set_read_cmd(mtestADDR,mtestBurstType,mtestID,
 mtestBurstLength,mtestDataSize);
mst_agent.rd_driver.send(rd_transaction);

`timescale 1ns / 1ps

import axi_vip_pkg::*;
import axi_demo_axi_vip_0_0_pkg::*;

module tb_top();

bit clk;
bit aresetn;

//used in API and parital randomization for transaction generation and data read back from driver
axi_transaction                         wr_transaction;                // Write transaction
axi_transaction                         rd_transaction;                // Read transaction

xil_axi_uint                            mtestWID;                      // Write ID  
xil_axi_ulong                           mtestWADDR;                    // Write ADDR  
xil_axi_len_t                           mtestWBurstLength;             // Write Burst Length   
xil_axi_size_t                          mtestWDataSize;                // Write SIZE  
xil_axi_burst_t                         mtestWBurstType;               // Write Burst Type  
xil_axi_uint                            mtestRID;                      // Read ID  
xil_axi_ulong                           mtestRADDR;                    // Read ADDR  
xil_axi_len_t                           mtestRBurstLength;             // Read Burst Length   
xil_axi_size_t                          mtestRDataSize;                // Read SIZE  
xil_axi_burst_t                         mtestRBurstType;               // Read Burst Type  
xil_axi_lock_t                          mtestLOCK;                     // LOCK value for WRITE/READ_BURST transaction
xil_axi_cache_t                         mtestCacheType = 3;            // Cache Type value for WRITE/READ_BURST transaction
xil_axi_prot_t                          mtestProtectionType = 3'b000;  // Protection Type value for WRITE/READ_BURST transaction
xil_axi_region_t                        mtestRegion = 4'b000;          // Region value for WRITE/READ_BURST transaction
xil_axi_qos_t                           mtestQOS = 4'b000;             // QOS value for WRITE/READ_BURST transaction
xil_axi_data_beat                       dbeat;                         // Data beat value for WRITE/READ_BURST transaction
xil_axi_user_beat                       usrbeat;                       // User beat value for WRITE/READ_BURST transaction
xil_axi_data_beat [255:0]               mtestWUSER;                    // Wuser value for WRITE/READ_BURST transaction
xil_axi_data_beat                       mtestAWUSER = 'h0;             // Awuser value for WRITE/READ_BURST transaction
xil_axi_data_beat                       mtestARUSER = 0;               // Aruser value for WRITE/READ_BURST transaction
xil_axi_data_beat [255:0]               mtestRUSER;                    // Ruser value for WRITE/READ_BURST transaction
xil_axi_uint                            mtestBUSER = 0;                // Buser value for WRITE/READ_BURST transaction
xil_axi_resp_t                          mtestBresp;                    // Bresp value for WRITE/READ_BURST transaction
xil_axi_resp_t[255:0]                   mtestRresp;                    // Rresp value for WRITE/READ_BURST transaction

bit [63:0]                             mtestWData;                     // Write Data
bit[8*4096-1:0]                        Wdatablock;                     // Write data block
xil_axi_data_beat                      Wdatabeat[];                    // Write data beats

bit [63:0]                             mtestRData;                     // Read Data
bit[8*4096-1:0]                        Rdatablock;                     // Read data block
xil_axi_data_beat                      Rdatabeat[];                    // Read data beats


  initial begin
    aresetn = 1'b0;
    clk = 1'b0;
    #100ns;
    aresetn = 1'b1;
  end
   
  always #10 clk <= ~clk;

axi_demo u_dut(
    .aclk_0       (clk     ),
    .aresetn_0    (aresetn )
);

axi_demo_axi_vip_0_0_mst_t              mst_agent;

initial begin
    mst_agent = new("master vip agent",u_dut.axi_vip_0.inst.IF);
    mst_agent.start_master();               // mst_agent start to run
    mtestWID = $urandom_range(0,(1<<(0)-1)); 
    mtestWADDR = 'hc000_1000;//$urandom_range(0,(1<<(32)-1));
    mtestWBurstLength = 0;
    mtestWDataSize = xil_axi_size_t'(xil_clog2((32)/8));
    mtestWBurstType = XIL_AXI_BURST_TYPE_INCR;
    mtestWData = 'h12345678;//$urandom();
    $display("mtestWDataSize = %d", mtestWDataSize);
    //single write transaction filled in user inputs through API 
    single_write_transaction_api("single write with api",
                                 .id(mtestWID),
                                 .addr(mtestWADDR),
                                 .len(mtestWBurstLength), 
                                 .size(mtestWDataSize),
                                 .burst(mtestWBurstType),
                                 .wuser(mtestWUSER),
                                 .awuser(mtestAWUSER), 
                                 .data(mtestWData)
                                 );
                                  
    mtestRID = $urandom_range(0,(1<<(0)-1));
    mtestRADDR = mtestWADDR;
    mtestRBurstLength = 0;
    mtestRDataSize = xil_axi_size_t'(xil_clog2((32)/8)); 
    mtestRBurstType = XIL_AXI_BURST_TYPE_INCR;
    
    $display("mtestRDataSize = %d", mtestRDataSize);
    //single read transaction filled in user inputs through API 
    single_read_transaction_api("single read with api",
                                 .id(mtestRID),
                                 .addr(mtestRADDR),
                                 .len(mtestRBurstLength), 
                                 .size(mtestRDataSize),
                                 .burst(mtestRBurstType)
                                 );
end

  task automatic single_write_transaction_api ( 
                                input string                     name ="single_write",
                                input xil_axi_uint               id =0, 
                                input xil_axi_ulong              addr =0,
                                input xil_axi_len_t              len =0, 
                                input xil_axi_size_t             size =xil_axi_size_t'(xil_clog2((32)/8)),
                                input xil_axi_burst_t            burst =XIL_AXI_BURST_TYPE_INCR,
                                input xil_axi_lock_t             lock = XIL_AXI_ALOCK_NOLOCK,
                                input xil_axi_cache_t            cache =3,
                                input xil_axi_prot_t             prot =0,
                                input xil_axi_region_t           region =0,
                                input xil_axi_qos_t              qos =0,
                                input xil_axi_data_beat [255:0]  wuser =0, 
                                input xil_axi_data_beat          awuser =0,
                                input bit [63:0]              data =0
                                                );
    axi_transaction                               wr_trans;
    $display("single_write_transaction_api size = %d", size);
    wr_trans = mst_agent.wr_driver.create_transaction(name);
    wr_trans.set_write_cmd(addr,burst,id,len,size);
    wr_trans.set_prot(prot);
    wr_trans.set_lock(lock);
    wr_trans.set_cache(cache);
    wr_trans.set_region(region);
    wr_trans.set_qos(qos);
    wr_trans.set_data_block(data);
    mst_agent.wr_driver.send(wr_trans);   
  endtask  : single_write_transaction_api	
	
  task automatic single_read_transaction_api ( 
                                    input string                     name ="single_read",
                                    input xil_axi_uint               id =0, 
                                    input xil_axi_ulong              addr =0,
                                    input xil_axi_len_t              len =0, 
                                    input xil_axi_size_t             size =xil_axi_size_t'(xil_clog2((32)/8)),
                                    input xil_axi_burst_t            burst =XIL_AXI_BURST_TYPE_INCR,
                                    input xil_axi_lock_t             lock =XIL_AXI_ALOCK_NOLOCK ,
                                    input xil_axi_cache_t            cache =3,
                                    input xil_axi_prot_t             prot =0,
                                    input xil_axi_region_t           region =0,
                                    input xil_axi_qos_t              qos =0,
                                    input xil_axi_data_beat          aruser =0
                                                );
    axi_transaction                               rd_trans;
    $display("single_read_transaction_api size = %d", size);
    rd_trans = mst_agent.rd_driver.create_transaction(name);
    rd_trans.set_read_cmd(addr,burst,id,len,size);
    rd_trans.set_prot(prot);
    rd_trans.set_lock(lock);
    rd_trans.set_cache(cache);
    rd_trans.set_region(region);
    rd_trans.set_qos(qos);
    mst_agent.rd_driver.send(rd_trans);   
  endtask  : single_read_transaction_api

endmodule

/*————————————————
版权声明：本文为CSDN博主「张海军2013」的原创文章，遵循CC 4.0 BY-SA版权协议，转载请附上原文出处链接及本声明。
原文链接：https://blog.csdn.net/zhanghaijun2013/article/details/131948341
*/