sv program module

为了避免races，在验证中引入program；

Similarities between program and module block

1. A program block can instantiate another program block in the way how the module is instantiated another module block.
2. Both can have no or more inputs, inout, and output ports.
3. Both can have tasks, functions, variable declaration.
4. Both can have continuous assignments, initial blocks, concurrent assertions, generate blocks, etc.

Difference between program and module block

1. A program block can not instantiate a module block. On the opposite side, a module block can instantiate another module or program block.
2. A program block can not have an interface, user-defined primitives (UDP), always block or nested program.
3. The initial block inside the program block is scheduled in the reactive region whereas the initial blocks inside the module lock are scheduled in the active region.

tips

• program 用在验证； 而module用在design；
• program一般在top引用；
• program 不能用always ； primitives； UDPs ，例化模块； interface； 包含其他program
• It shall not contain always procedures,
  primitives, UDPs, or declarations or instances of modules, interfaces, or other programs
• References to program signals from outside any program block shall be an error
• Nested programs with no ports or top-level programs that are not
  explicitly instantiated are implicitly instantiated once. Implicitly instantiated programs have the same
  instance and declaration name.

https://vlsiverify.com/system-verilog/program-block/

//+++++++++++++++++++++++++++++++++++++++++++++++++
// Simple Program with ports
//+++++++++++++++++++++++++++++++++++++++++++++++++
program simple(input wire clk,output logic reset,
            enable, input logic [3:0] count);
  //=================================================
  // Initial block inside program block
  //=================================================
  initial begin
    $monitor("@%0dns count = %0d",$time,count);
    reset = 1;
    enable = 0;
    #20 reset = 0;
    @ (posedge clk);
    enable = 1;
    repeat (5) @ (posedge clk);
    enable = 0;
    // Call task in module
    simple_program.do_it();
  end
  //=================================================
  // Task inside a module
  //=================================================
  task do_it();
    $display("%m I am inside program");
  endtask

endprogram
//=================================================
//  Module which instanciates program block
//=================================================
module simple_program();
logic clk  = 0;
always #1 clk ++;
logic [3:0] count;
wire reset,enable;
//=================================================
// Simple up counter
//=================================================
always @ (posedge clk)
 if (reset) count <= 0;
 else if (enable) count ++;
//=================================================
// Program is connected like a module
//=================================================
simple prg_simple(clk,reset,enable,count);
//================================================
=
// Task inside a module
//=================================================
task do_it();
  $display("%m I am inside module");
endtask
//=================================================
// Below code is illegal
//=================================================
//initial begin
//  prg_simple.do_it();
//end

endmodule