目录
摘要:verilog中的module用于描述 硬件,它可以始终包含initial和assign语句。SV引入了program,其中包含了完整的测试平台 。
1. program与module
- program 的目的:
-
- 为testbench提供接入点;
- 创建了一个域来封装program的数据、任务和函数;
- 便于资源在Reactive region的调度。
-
- program不能包含always块;
- program可以有ports,interfaces,final,initial statement;
- program可以调用modul中的函数和方任务,而module则不可以调用program中 的任务和函数 。
1 //+++++++++++++++++++++++++++++++++++++++++++++++++
2 // Simple Program with ports
3 //+++++++++++++++++++++++++++++++++++++++++++++++++
4 program simple(input wire clk,output logic reset,
5 enable, input logic [3:0] count);
6 //=================================================
7 // Initial block inside program block
8 //=================================================
9 initial begin
10 $monitor("@%0dns count = %0d",$time,count);
11 reset = 1;
12 enable = 0;
13 #20 reset = 0;
14 @ (posedge clk);
15 enable = 1;
16 repeat (5) @ (posedge clk);
17 enable = 0;
18 // Call task in module
19 simple_program.do_it();
20 end
21 //=================================================
22 // Task inside a module
23 //=================================================
24 task do_it();
25 $display("%m I am inside program");
26 endtask
27
28 endprogram
29 //=================================================
30 // Module which instanciates program block
31 //=================================================
32 module simple_program();
33 logic clk = 0;
34 always #1 clk ++;
35 logic [3:0] count;
36 wire reset,enable;
37 //=================================================
38 // Simple up counter
39 //=================================================
40 always @ (posedge clk)
41 if (reset) count <= 0;
42 else if (enable) count ++;
43 //=================================================
44 // Program is connected like a module
45 //=================================================
46 simple prg_simple(clk,reset,enable,count);
47 //=================================================
48 // Task inside a module
49 //=================================================
50 task do_it();
51 $display("%m I am inside module");
52 endtask
53 //=================================================
54 // Below code is illegal
55 //=================================================
56 //initial begin
57 // prg_simple.do_it();
58 //end
59
60 endmodule
61
62 //compile result
63
64 @0ns count = x
65 @1ns count = 0
66 @23ns count = 1
67 @25ns count = 2
68 @27ns count = 3
69 @29ns count = 4
70 simple_program.do_it I am inside module
71 @31ns count = 5
2. progam control tasks
- SV引入 $exit 来关闭当前程序以及其衍生的所有线程。
- 默认情况下,当程序运行到initial块末尾时,$exit会被自动调用。
1 //+++++++++++++++++++++++++++++++++++++++++++++++++
2 // Simple Program with ports
3 //+++++++++++++++++++++++++++++++++++++++++++++++++
4 program exit_simple(input wire clk,output logic reset,
5 enable, input logic [3:0] count);
6 //=================================================
7 // Initial block inside program block
8 //=================================================
9 initial begin
10 $monitor("@%0dns count = %0d",$time,count);
11 fork
12 do_something();
13 join_none
14 reset = 1;
15 enable = 0;
16 #20 reset = 0;
17 @ (posedge clk);
18 enable = 1;
19 repeat (5) @ (posedge clk);
20 enable = 0;
21 #10 $exit();
22 #100 $display("%0dns Terminating simulation", $time);
23 $finish;
24 end
25 //=================================================
26 // Simple task
27 //=================================================
28 task do_something();
29 while (1) begin
30 #5 $display("%0dns inside do_something task", $time);
31 end
32 endtask
33
34 endprogram
35 //=================================================
36 // Module which instanciates program block
37 //=================================================
38 module exit_program();
39 logic clk = 0;
40 always #1 clk ++;
41 logic [3:0] count;
42 wire reset,enable;
43 //=================================================
44 // Simple up counter
45 //=================================================
46 always @ (posedge clk)
47 if (reset) count <= 0;
48 else if (enable) count ++;
49 //=================================================
50 // Program is connected like a module
51 //=================================================
52 exit_simple prg_simple(clk,reset,enable,count);
53
54 endmodule
55
56 //compile result
57
58 @0ns count = x
59 @1ns count = 0
60 5ns inside do_something task
61 10ns inside do_something task
62 15ns inside do_something task
63 20ns inside do_something task
64 @23ns count = 1
65 25ns inside do_something task
66 @25ns count = 2
67 @27ns count = 3
68 @29ns count = 4
69 30ns inside do_something task
70 @31ns count = 5
71 35ns inside do_something task
72 40ns inside do_something task
3. program with interface
使用interface处理大量接口的连接问题。
1 //+++++++++++++++++++++++++++++++++++++++++++++++++
2 // Define the interface
3 //+++++++++++++++++++++++++++++++++++++++++++++++++
4 interface mem_if (
5 input wire clk,
6 output logic reset,
7 output logic enable,
8 input wire [3:0] count
9 );
10 endinterface
11 //+++++++++++++++++++++++++++++++++++++++++++++++++
12 // Simple Program with ports
13 //+++++++++++++++++++++++++++++++++++++++++++++++++
14 program if_program(mem_if mem);
15 //=================================================
16 // Initial block inside program block
17 //=================================================
18 initial begin
19 $monitor("@%0dns count = %0d",$time,mem.count);
20 mem.reset = 1;
21 mem.enable = 0;
22 #20 mem.reset = 0;
23 @ (posedge mem.clk);
24 mem.enable = 1;
25 repeat (5) @ (posedge mem.clk);
26 mem.enable = 0;
27 end
28 endprogram
29 //=================================================
30 // Module which instanciates program block
31 //=================================================
32 module simple_program();
33 logic clk = 0;
34 always #1 clk ++;
35 logic [3:0] count;
36 wire reset,enable;
37 //=================================================
38 // Connect the interface
39 //=================================================
40 mem_if inf(
41 .clk (clk) ,
42 .reset (reset) ,
43 .enable (enable),
44 .count (count)
45 );
46 //=================================================
47 // Simple up counter
48 //=================================================
49 always @ (posedge clk)
50 if (reset) count <= 0;
51 else if (enable) count ++;
52 //=================================================
53 // Program is connected like a module
54 //=================================================
55 if_program prg_simple(
56 .mem (inf)
57 );
58 endmodule
59
60 //compile result
61
62 @0ns count = x
63 @1ns count = 0
64 @23ns count = 1
65 @25ns count = 2
66 @27ns count = 3
67 @29ns count = 4
68 @31ns count = 5