基于有限状态机的自动售货机控制电路

1、该售货机的功能为每件商品25元，投入总金额大于25元时可找回零钱。（如图为状态转移图）
2、使用VHDL实现

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity veding_machine is
	port(clk,rst: in std_logic;
	nickel_in,dime_in,quarter_in : in std_logic;
	candy_out,nickel_out,dime_out:out std_logic);
end veding_machine;
-------------------------------------------------
architecture Behavioral of veding_machine is
	type state is (st0,st5,st10,st15,st20,st25,st30,st35,st40,st45);
	signal present_state,next_state : state;
begin
	process (rst,clk)
	begin
		if(rst='1') then 
			present_state <= st0;
		elsif(clk'event and clk ='1')then
			present_state<= next_state;
		end if;
	end process;
-------------------------------------
process(present_state,nickel_in,dime_in,quarter_in)
begin
	case present_state is
		when st0 =>
			candy_out <= '0';
			nickel_out <='0';
			dime_out <='0';
			if (nickel_in= '1') then next_state <= st5;
			elsif(dime_in= '1') then next_state<= st10;
			elsif(quarter_in= '1') then next_state <= st25;
			else next_state <= st0;
			end if ;
		when st5 =>
			candy_out <= '0';
			nickel_out <='0';
			dime_out <='0';
			if (nickel_in= '1') then next_state <= st10;
			elsif(dime_in= '1') then next_state<= st15;
			elsif(quarter_in= '1') then next_state <= st30;
			else next_state <= st5;
			end if ;
		when st10 =>
			candy_out <= '0';
			nickel_out <='0';
			dime_out <='0';
			if (nickel_in= '1') then next_state <= st15;
			elsif(dime_in= '1') then next_state<= st20;
			elsif(quarter_in= '1') then next_state <= st35;
			else next_state <= st10;
			end if ;
		when st15 =>
			candy_out <= '0';
			nickel_out <='0';
			dime_out <='0';
			if (nickel_in= '1') then next_state <= st20;
			elsif(dime_in= '1') then next_state<= st25;
			elsif(quarter_in= '1') then next_state <= st40;
			else next_state <= st15;
			end if ;
		when st20 =>
			candy_out <= '0';
			nickel_out <='0';
			dime_out <='0';
			if (nickel_in = '1') then next_state <= st25;
			elsif(dime_in= '1') then next_state<= st30;
			elsif(quarter_in= '1') then next_state <= st35;
			else next_state <= st20;
			end if ;
		when st25 =>
			candy_out <= '1';
			nickel_out <='0';
			dime_out <='0';
			next_state <= st0;
		when st30 =>
			candy_out <= '1';
			nickel_out <='1';
			dime_out <='0';
			next_state <= st0;
		when st35 =>
			candy_out <= '1';
			nickel_out <='0';
			dime_out <='1';
			next_state <= st0;
		when st40 =>
			candy_out <= '0';
			nickel_out <='1';
			dime_out <='0';
			next_state <= st35;
		when st45 =>
			candy_out <= '0';
			nickel_out <='0';
			dime_out <='1';
			next_state <= st35;
	end case;
end process;
end Behavioral;

3、生成原理图

4、添加testbench在modelsim中仿真

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_candy IS
END tb_candy;
 
ARCHITECTURE behavior OF tb_candy IS 

    COMPONENT veding_machine
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         nickel_in : IN  std_logic;
         dime_in : IN  std_logic;
         quarter_in : IN std_logic;
         candy_out : OUT  std_logic;
         nickel_out : OUT  std_logic;
         dime_out : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal nickel_in : std_logic;
   signal dime_in : std_logic;
   signal quarter_in : std_logic;

 	--Outputs
   signal candy_out : std_logic;
   signal nickel_out : std_logic;
   signal dime_out : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN

   uut: veding_machine PORT MAP (
          clk => clk,
          rst => rst,
          nickel_in => nickel_in,
          dime_in => dime_in,
          quarter_in => quarter_in,
          candy_out => candy_out,
          nickel_out => nickel_out,
          dime_out => dime_out
        );

   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   stim_proc: process
   begin		
	  rst <= '1';
      wait for 10 ns;	
		rst <= '0';
      wait;
   end process;
   
buy_candy: process
   begin 
   nickel_in <= '1';
   dime_in <= '0';
   quarter_in <= '0';
   wait for 40 ns;
   nickel_in <= '0';
   dime_in <= '1';
   quarter_in <= '0';
   wait for 40 ns;
   nickel_in <= '0';
   dime_in <= '0';
   quarter_in <= '1';
   wait;
  end process;
END;

查看仿真波形：