Verilog代码
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 15:34:29 04/21/2018
// Design Name:
// Module Name: LAB12
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module LAB12(
input [7:0] a,
input [7:0] b,
output reg equ,
output reg m
);
always@(a or b)
if (a>b)
begin
equ = 0;
m = 1;
end
else if(a<b)
begin
equ = 0;
m = 0;
end
else
begin
equ = 1;
m = 0;
end
endmodule
仿真代码
`timescale 1ns / 1ps
// Company:
// Engineer:
//
// Create Date: 16:40:08 04/21/2018
// Design Name: LAB12
// Module Name: D:/Xilinx/LAB12/test12.v
// Project Name: LAB12
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for