要求:使用时序逻辑对一个单比特信号进行毛刺滤除,高电平或者低电平宽度小于4个认为是毛刺
//毛刺滤除
//使用时序逻辑对一个单比特信号进行毛刺滤除,高电平或者低电平宽度小于4个认为是毛刺
module filter(
input sys_clk,
input sys_res,
input data_in,
output reg data_out
);
parameter M = 4;
reg [2:0]data_buff;
reg [1:0]cnt;
wire r_d; //检测到上升沿或者下降沿
always@(posedge sys_clk or negedge sys_res)begin
if(!sys_res)
data_buff <= 'd0;
else
data_buff <= {data_buff[1:0],data_in};
end
assign r_d = (data_buff[1] & (~data_buff[2]))|((~data_buff[1]) & data_buff[2]);
always@(posedge sys_clk or negedge sys_res)begin
if(!sys_res)
cnt <= 'd0;
else if(r_d == 1'b1)
cnt <= 'd0;
else
cnt <= cnt + 1'b1;
end
always@(posedge sys_clk or negedge sys_res)begin
if(!sys_res)
data_out <= 1'b0;
else if(cnt == M-1)
data_out <= data_buff[1];
end
endmodule
`timescale 1ns/1ns
module tb();
reg clk;
reg res;
reg data_in;
wire data_out;
reg [6:0] cnt;
initial begin
clk <= 1'b0;
res <= 1'b0;
#100 res <= 1'b1;
end
always #10 clk <= ~clk;
always@(posedge clk or negedge res)
if(!res)
cnt <= 'd0;
else
cnt <= cnt + 1;
always@(posedge clk or negedge res)
if(!res)
data_in <= 1'b0;
else if((cnt >= 'd1 && cnt <= 'd15)||(cnt >= 'd51 && cnt <= 'd70)||(cnt >= 'd100 && cnt <= 'd108))
data_in <= {$random}%2; //随机产生0或1
else if(cnt == 'd50)
data_in <= 1'b1;
else if(cnt >= 'd90)
data_in <= 1'b0;
filter u_filter(
. sys_clk (clk) ,
. sys_res (res) ,
. data_in (data_in) ,
. data_out (data_out)
);
endmodule