单bit信号进行毛刺滤除（Verilog）

RTL代码：

module filter(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
);
	reg data_in_r;
	wire data_edge;
	reg [2:0]cnt;
	
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			data_in_r <= 1'b0;
		else
			data_in_r <= data_in;
	end 
	
	assign data_edge = data_in ^ data_in_r;
	
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			cnt <= 'd0;
		else if(data_edge)
			cnt <= 'd0;
		else 
			cnt <= cnt + 1'b1;
	end
	
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			data_out <= 1'b0;
		else if(&cnt)
			data_out <= data_in_r;
		else
			data_out <= data_out;
	end

endmodule 

RTL视图：