基于BD和video IP 构建Video System时的边界桥接模块（video_in video_out VTC）

视频信号输入时，是video format，
通常由video clk 为工作时钟，数据指示信号，包括
vsync, hsync, datavalid，

而video IP则通常接受AXIS接口的视频流信号输入，经过处理后，输出AXIS接口的视频流信号给下一级的video IP。
最后输出时，再转换成video format向外部其他模块输出。
从AXIS接口的视频流中，重建
vsync, hsync, datavalid。

这时，就需要使用bridge IP。
即Video In to AXIS核以及 AXIS to Video Out 核。

下面分别介绍这些桥接模块。

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Video In to AXIS核
这个核有两个时钟域，vid_clk和aclk。
vid_clk是像素时钟，aclk是AXIS的接口时钟，
通常要求aclk 大于或者等于vid_clk，从而减小FIFO的尺寸，提高性能。

When the core is in common clock mode, there is only a single reset input port aresetn
that is used to reset both the AXI4-Stream output and Video input sides of the bridge.
In independent clock mode, an additional reset port vid_io_in_reset is used to reset the
Video output side of the bridge.
Resets must be synchronous to their respective clock domains.
asserting either reset causes the FIFO to be flushed.
When asserted, the reset should be held for at least two
clock periods of the lowest frequency clock

To support standard definition video input such as PAL and NTSC,
the video input has a vid_field_id bit as part of its interface and embedded vertical blanks and horizontal blanks.
The VTC has a corresponding vid_field_id pin defined for this purpose.

The Video In to AXI4-Stream core has a frame ID output, fid, timed to the AXI4-Stream bus.
Some cores that use this fid bit are the AXI4-Stream to Video Out, VDMA, and Video Deinterlacer cores.
The AXI4-Stream to Video Out core has a field ID input, fid, sampled in time with the AXI4-Stream input bus.
This fid bit must be asserted by the upstream source of AXI4-Stream video.

For systems with a frame buffer, the field ID input can come from any core containing a
frame buffer. The field ID from the Video In to AXI4-Stream core can be used by the frame
buffer if necessary,

the Video In to AXI4-Stream can provide the field bit directly to the AXI4-Stream to Video Out core if no intervening frame buffer exists.

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AXIS to Video Out 核。
这个核有两个时钟域，vid_clk和aclk。
vid_clk是像素时钟，aclk是AXIS的接口时钟，
通常要求aclk 大于或者等于vid_clk，从而减小FIFO的尺寸，提高性能。

The core is designed to be used in parallel with the generator functionality of the VTC.
There are two timing modes supported: slave and master timing mode.
In general, it is recommended to use the slave timing mode to minimize buffering and latency requirements.

It is recommended that the Xilinx Video Timing Controller be configured to
output all syncs and blanks (horizontal sync, horizontal blank, vertical sync, vertical blank,
and active video).

The independent clocking mode is used when the bridge requires asynchronous and independent clocks for the native and AXI4-Stream sides of the bridge.

The video output clock corresponds to the video line standard used on the input.
and by the corresponding Video Timing Controller core that is used to detect video timing.

In slave mode, the VTC generator is a slave to the Video Out core which controls it through
clock enable.
In master mode, the VTC is the timing master for the output side of the VDMA,
the output processing cores, and the Video Out core.

In master mode, the Video Out core does not control the VTC generator timing; instead, it uses the VTC timing as a reference, and synchronizes the video pipeline to it.

The main difference between slave and master timing mode is how the FIFO and/or VTC is used to align the pixels with the video timing signals.

In slave timing mode, the output sync section controls both the reading of the FIFO and the
VTC (by halting it). In master timing mode, the VTC generator is never halted. Only the
reading of the FIFO is controlled by the output synchronizer module.

Pulsing the Fsync signal causes the VTC timing to be reset on demand.

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Video Timing Controller

The output can be the same format or a different format as the detected input. This allows detecting one format and generating a different format.

The Video Timing Controller core supports up to 16 frame sync output signals.

clk ---- Video Core Clock
det_clken ----Video Timing Detection Core active-High Clock Enable
gen_clken ----Video Timing Generator Core active-High Clock Enable
resetn----Video Core active-Low Synchronous Reset
irq ---- Interrupt request output, active-High edge

field_id_in----Used to set the field_id polarity in the Detector Polarity Register
hsync_in----Used to set the DETECTOR HSYNC register
hblank_in----Used to set the DETECTOR HSIZE register
vsync_in----Used to set the DETECTOR F0_VSYNC_V and the F0_VSYNC_H registers.
vblank_in----Used to set the DETECTOR_VSIZE and the F0_VBLANK_H registers.
active_video_in----Used to set the DETECTOR ACTIVE_SIZE register.
active_chroma_in ----Used to set the VIDEO_FORMAT and the CHROMA_PARITY bits in the Detector Encoding Register.

field_id_out----
Generated field id signal. Polarity configured by the Generator Polarity Register
hsync_out----
Generated horizontal synchronization signal. Polarity configured by
the control register. Asserted active during the cycle set by the
HSYNC_START bits and deasserted during the cycle set by the
HSYNC_END bits in the GENERATOR HSYNC register.
hblank_out----
Generated horizontal blank signal. Polarity configured by the
control register. Asserted active during the cycle set by
ACTIVE_HSIZE and deasserted during the cycle set by the
FRAME_HSIZE bits in the GENERATOR HSIZE register.
vsync_out----
Generated vertical synchronization signal. Polarity configured by the
control register. Asserted active during the line set by the
F#_VSYNC_VSTART bits and deasserted during the line set by the
F#_VSYNC_VEND bits in the GENERATOR F#_VSYNC_V registers.
vblank_out----
Generated vertical blank signal. Polarity configured by the control
register. Asserted active during the line set by the ACTIVE_VSIZE bits
and deasserted during the line set by the GENERATOR VSIZE
register.
active_video_out----
Generated active video signal. Polarity configured by the control
register. Active for non blanking lines. Asserted active during the
first cycle of the field/frame and deasserted during the cycle set by
the GENERATOR ACTIVE_SIZE register
active_chroma_out----
Generated active chroma signal. Denotes which lines contain valid
chroma samples (used for YUV 4:2:0). Polarity configured by the
GENERATOR POLARITY register. Active for non-blanking lines
configured y the VIDEO_FORMAT and the CHROMA_PARITY bits in
the GENERATOR Encoding Register.

fsync_out----
Each Frame Synchronization bit toggles for only one clock cycle
during each frame. The number of bits is configured with the Frame
Syncs GUI parameter.
Each bit is independently configured for horizontal and vertical
clock cycle position with the Frame Sync 0-15 Config registers).

fsync_in----
This is a one clock cycle pulse (active-High) input. The video timing
generator will be synchronized to the input if used.
The fsync_in should be driven High for only one clock cycle per frame.
This resets all internal generator counters and starts the generated frame timing
synchronized to this input.
If the fsync_in input is used, then the detector must be disabled.
if the detector is used, then the fsync_in pin must be driven to ‘0’.

sof_state----
Indicates AXI4Stream start of Frame. When used with the AXI4 Video
Out bridge, connect the sof_state output port of the bridge to the
input sof_state of VTC.

The RESETn signal only resets the video timing interfaces and processing of the core. The
AXI4-Lite interface is unaffected by the RESETn signal to allow the video timing processing
core to be reset without halting the AXI4-Lite interface. However, if the RESETn is asserted
Low during an AXI4-Lite register read or write, the AXI4-Lite interface asserts the slave error
response (0x2) for all addresses.

The S_AXI_ARESETn signal resets the
entire core including the AXI4-Lite and video timing interfaces.

the psreset generator has to ensure all signals are asserted/de-asserted long enough so that all interfaces and clock-domains are correctly reinitialized.

By default, the blanking signal rises at the same clock edge the last active video signal (of a frame) falls and falls at the same clock edge the first active video signal (of a frame) rises.
Also by default, the vsync signals rises and falls at the same clock edge as a rising edge of the Nth rising edge of the hblank signal.
Both behaviors are because only the Vertical timing in Lines count are configured, not in pixel count, defined in the video timing specifications.
you might want to slightly change the configuration to move the Vertical blanking or Sync signals. Use the Horizontal Fine Adjustment Settings to do so.

GUI parameters:

Synchronize Generator to Detector or to fsync_in----
When selected,
the timing generator automatically synchronizes to the detector or to the fsync_in input port. Otherwise, the generator runs in free-run mode.

Frame Syncs----
This parameter sets the number of frame synchronization outputs to
generate and supports up to 16 independent outputs.

Auto Generation Mode----
When enabled, this parameter will cause the generated
video timing outputs to change based on the detected inputs.
If this parameter is disabled, the video timing outputs will be generated based on only the first
detected input format.
The output for the generated synchronization signals will continue even if the detection block loses lock.
This parameter is available only if both the Enable Generation and Enable Detection parameters are both enabled.
Note: This parameter has an effect only if one or more of the source select control register bits are set to Low.

Video Mode----
This parameter sets the default video format and controls the Horizontal, Vertical and Horizontal Fine Adjustment settings below.
Values of 720p, 480p, 1080p, or Custom are valid. The interlaced video modes of 1080i, 480i and 576i are also available when the Interlaced Support parameter is checked.
Video Modes are removed or added to this list based upon the sizes selected in the Max Clocks per Line and Max Lines per Frame parameters.

Chroma Format----
This parameter sets the default value of the video format in the GENERATOR ENCODING register at address offset 0x68.
This controls the behavior of the active_chroma_out output port.

Chroma Parity----
This parameter sets the default value of the chroma parity in the GENERATOR ENCODING register at address offset 0x68.
This controls the behavior of the active_chroma_out output port.