Hdlbits
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状态图 有限状态机
6-146-15z1z2目前总结的规律1. s0状态与检测序列的第一位相反2. 检测序列重叠还是不重叠不同在于最后一个状态的变化原创 2021-06-21 15:57:16 · 1347 阅读 · 0 评论 -
Q8:Design a Mealy FSM(Exams/ece241 2013 q8)
题目Implement a Mealy-type finite state machine that recognizes the sequence “101” on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the “101” sequence is detected. Your FSM should also have an active-low原创 2021-06-21 15:00:23 · 386 阅读 · 0 评论 -
Fsm hdlc HDLbits
题目Synchronous HDLC framing involves decoding a continuous bit stream of data to look for bit patterns that indicate the beginning and end of frames (packets). Seeing exactly 6 consecutive 1s (i.e., 01111110) is a “flag” that indicate frame boundaries. To原创 2021-06-21 14:10:38 · 513 阅读 · 0 评论 -
Lemmings2 HDLbits
题目:module top_module( input clk, input areset, // Freshly brainwashed Lemmings walk left. input bump_left, input bump_right, input ground, output walk_left, output walk_right, output aaah ); parameter LEFT = 0, RI原创 2021-06-19 20:26:24 · 207 阅读 · 0 评论 -
Lemmings1 HDLbits
题目:The game Lemmings involves critters with fairly simple brains. So simple that we are going to model it using a finite state machine.In the Lemmings’ 2D world, Lemmings can be in one of two states: walking left or walking right. It will switch directio原创 2021-06-18 16:53:54 · 130 阅读 · 0 评论 -
Fsm3onehot HDLbits 独热编码
题目:The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following one-hot state encoding: A=4’b0001, B=4’b0010, C=4’b0100, D=4’b1000.Derive state transition and output logic equations原创 2021-06-18 14:02:50 · 482 阅读 · 0 评论 -
Fsm1 HDLbits
题目:This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.This exercise is the same as fsm1s, but using asynchronous reset.module top_module( input clk, input are原创 2021-06-18 13:59:17 · 347 阅读 · 0 评论 -
Countbcd HDLbits
题目:Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three digits shoul原创 2021-06-17 14:33:12 · 441 阅读 · 0 评论 -
Count10 计数器
题目:module top_module ( input clk, input reset, // Synchronous active-high reset output reg [3:0] q); always@(posedge clk) begin if(reset) q <= 0; else begin if (q == 9)原创 2021-06-14 17:40:24 · 1222 阅读 · 0 评论 -
Edgecapture的收获
题目:For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. “Capture” means that the output will remain 1 until the register is reset (synchronous reset).Each output bit behaves like a SR flip-flop:原创 2021-06-14 17:21:37 · 438 阅读 · 0 评论 -
HDLbits Popcount3的一点疑问
题目:A “population count” circuit counts the number of '1’s in an input vector. Build a population count circuit for a 3-bit input vector.module top_module( input [2:0] in, output [1:0] out ); reg [1:0] out1; integer i; always@(*)原创 2021-06-13 11:22:07 · 1112 阅读 · 4 评论