Fsm1 HDLbits

题目：
This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.
This exercise is the same as fsm1s, but using asynchronous reset.

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

	// 定义状态
    parameter A=0, B=1; 
    // 定义现态、次态
    reg state, next_state;

    always @(*) begin    // This is a combinational always block
        // State transition logic
        case(state)
                B: begin
                    next_state <= in? state:A;
                end
                    
                A: begin
                    next_state <= in? state:B;
                end
                default: next_state <= 0;
            endcase
    end

    always @(posedge clk or posedge areset) begin    // This is a sequential always block
        // State flip-flops with asynchronous reset
        if(areset)
            state <= B;
        else begin
            state <= next_state;
        end
    end

    // Output logic
    assign out = (state == B)? 1:0;

endmodule

总结

1. 定义状态、现态、次态
2. 状态方程变化写在always@(*)里
3. 现态与次态关系写always@(posedge clk)里
4. 输出assign赋值