Countbcd HDLbits

题目：
Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three digits should be incremented.
答案

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);

    wire [3:0] valid,q0,q1,q2,q3;
    assign valid = {{(q2 == 9)&&(q1 == 9)&&(q0 == 9)},{(q[7:4] == 9)&&(q[3:0] == 9)},{q0 == 9},1'b1};
    assign ena = {{(q2 == 9)&&(q1 == 9)&&(q0 == 9)},{(q[7:4] == 9)&&(q[3:0] == 9)},q[3:0] == 9};
    assign q = {q3,q2,q1,q0};
    
    count count0(clk,reset,q0,valid[0],1'b1);
    count count1(clk,reset,q1,valid[1],{(q[7:4] == 9)&&(q[3:0] == 9)});
    count count2(clk,reset,q2,valid[2],{(q2 == 9)&&(q1 == 9)&&(q0 == 9)});
    count count3(clk,reset,q3,valid[3],{(q3 == 9)&&(q2 == 9)&&(q1 == 9)&&(q0 == 9)});
        
    
endmodule

module count(clk,reset,q_a,vld,ena);
    input clk;
    input reset;
    input vld;
    input ena;
    output [3:0] q_a;
    
    always@(posedge clk) begin
        if(reset)
            q_a <= 4'd0;
        else if((q_a == 4'd9)&&(ena))
            q_a <= 0;
        else if (vld)begin
            q_a <= q_a + 1'b1;
        end
    end
endmodule

若例化如下：

count count0(clk,reset,q[3:0],valid[0],1'b1);

则有

这是因为count count0(clk,reset,q[3:0],valid[0],1’b1)与assign q = {q3,q2,q1,q0}重复赋值导致的
下面这么用没问题

 assign ena = {{(q2 == 9)&&(q1 == 9)&&(q0 == 9)},{(q[7:4] == 9)&&(q[3:0] == 9)},q[3:0] == 9};

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);

    wire [3:0] valid,q0,q1,q2,q3;
    assign valid = {{(q2 == 9)&&(q1 == 9)&&(q0 == 9)},{(q1 == 9)&&(q0 == 9)},{q0 == 9},1'b1};
    assign ena = {{(q2 == 9)&&(q1 == 9)&&(q0 == 9)},{(q1 == 9)&&(q0 == 9)},q0 == 9};
    //assign q = {q3,q2,q1,q0};
    assign {q3,q2,q1,q0} = q;
    
    count count0(clk,reset,q[3:0],valid[0],1'b1);
    count count1(clk,reset,q[7:4],valid[1],{(q1 == 9)&&(q0 == 9)});
    count count2(clk,reset,q[11:8],valid[2],{(q2 == 9)&&(q1 == 9)&&(q0 == 9)});
    count count3(clk,reset,q[15:12],valid[3],{(q3 == 9)&&(q2 == 9)&&(q1 == 9)&&(q0 == 9)});
        
    
endmodule

module count(clk,reset,q_a,vld,ena);
    input clk;
    input reset;
    input vld;
    input ena;
    output [3:0] q_a;
    
    always@(posedge clk) begin
        if(reset)
            q_a <= 4'd0;
        else if((q_a == 4'd9)&&(ena))
            q_a <= 0;
        else if (vld)begin
            q_a <= q_a + 1'b1;
        end
    end
endmodule

收获：

1. 拼接时，要表明常数的位宽

{{(q2 == 9)&&(q1 == 9)&&(q0 == 9)},{(q[7:4] == 9)&&(q[3:0] == 9)},{q0 == 9},1'b1}
不是
{{(q2 == 9)&&(q1 == 9)&&(q0 == 9)},{(q[7:4] == 9)&&(q[3:0] == 9)},{q0 == 9},1}

2. count count0(clk,reset,q[3:0],valid[0],1’b1)是可以的