system verilog整数除法计算时要注意的点

请看下面的代码

module test(
);

int a=1;
int b=2;
int c=3;
int d=4;

real e=0;

initial begin
    #1;
    e=a/d;
    $display("a is %d, d is %d, e is %f",a,d,e);
    #1;
    e=b/d;
    $display("b is %d, d is %d, e is %f",b,d,e);
    #1;
    e=c/d;
    $display("c is %d, d is %d, e is %f",c,d,e);
    #1;
    e=d/d;
    $display("d is %d, d is %d, e is %f",d,d,e);

    #1;
    e=1.0*a/d;
    $display("a is %d, d is %d, e is %f",a,d,e);
    #1;
    e=1.0*b/d;
    $display("b is %d, d is %d, e is %f",b,d,e);
    #1;
    e=1.0*c/d;
    $display("c is %d, d is %d, e is %f",c,d,e);
    #1;
    e=1.0*d/d;
    $display("d is %d, d is %d, e is %f",d,d,e);

end

endmodule

结果如下
a is 1, d is 4, e is 0.000000
b is 2, d is 4, e is 0.000000
c is 3, d is 4, e is 0.000000
d is 4, d is 4, e is 1.000000
a is 1, d is 4, e is 0.250000
b is 2, d is 4, e is 0.500000
c is 3, d is 4, e is 0.750000
d is 4, d is 4, e is 1.000000

所以system verilog的计算我们要注意两个点

1. 不是四舍五入，只要分子比分母小结果就是0，除法得到的结果就是0
2. 即使我们定义了结果e为real类型，但是计算结果依然与期望不符，所以sv计算是依据输入数据的类型

解决办法是在计算前面加上1.0*就可以了。