ASIC:Application Specific Integrated Circuit
FPGA:Field Programmable Gate Array
HDL: Hardware Description Languages
IP:Intellectual Property
LUT:Look-Up-Table
DFT: Design For Testability
BIST:Built In Self Test
ATPG:Automatic Test Pattern Generator
ATE:Automatic Test Equipment
STIL:Standard Test Interfance Language
LVS: Layout vs. Schematic
DRC:Design Rule Check
ERC:Electronic Rule Check
ECO: Engineering Change Order
GDSII:Graphics Design Standard Format II
PV:Physical Verication
CTS:Clock Tree Synthesis
MVS:Multi Voltage Supply
LEF :Library Exchange Format
DEF:Design Exchange Format
NLDM:Non-Linear Delay Model
CCS:Composite Current Source
OCV:On Chip Variation
SI:Signal Integrity
STA: Static Timing Analysis
SDC:Synopsys Design Constraints
SPEF:Standard Parasitic Extraction Format
SDF:Standard Delay Format
AT:Arrival Time
RAT:Required Arrival Time
.itf:interconnect technology format file
.tf:technology file