FPGA学习笔记2--4位全加器

module adder4(a,b,cin,cout,sum);
output [3:0]sum;
output cout;
input [3:0]a;
input [3:0]b;
input cin;
assign {cout,sum}=a+b+cin;

endmodule

仿真：

`timescale 1ns/1ns 
`include "full_adder1.v" 
module tb_full_adder1();
reg a;
reg b;
reg cin;
wire sum;
wire cout;
full_adder1 u1(.a(a),.b(b),.cin(cin),
.sum(sum),.cout(cout));
initial begin
a=1'b0;
b=1'b0;
cin=1'b0;
end
always #5 a=~a;
always #10 b=~b;
always # 15 cin=~cin;
endmodule