FPGA学习笔记3--4位计数器

module count(
input clk,
input rst,
output reg [3:0]out
);
always @(posedge clk or negedge rst)
begin
if(!rst)
out<=1'b0;
else out<=out+1'b1;
end

endmodule

`timescale 1ns/1ns
module tb_count();
reg clk;
reg rst;
wire [3:0]out;
count u1(.clk(clk),.rst(rst),.out(out));
initial begin
clk<=1'b0;
rst<=1'b0;
#50 rst<=1'b1;
#1000 $finish;
end
always #10 clk<=~clk;
endmodule