FPGA学习笔记26--非流水和流水的8位加法器

module adder8(
output reg cout,
output reg[7:0]sum,
input [7:0]ina,
input [7:0]inb,
input cin,
input clk); 


reg[7:0] tempa,tempb; 


reg tempc; 

always @(posedge clk) 

     begin 

      tempa=ina;  tempb=inb;  tempc=cin;            //输入数据锁存 

      end 

 always @(posedge clk) 

     begin 

      {cout,sum}=tempa+tempb+tempc; 

      end 

endmodule 

module pipeline(
output reg cout,
output reg [7:0]sum,
input [7:0]ina,
input [7:0]inb,
input cin,
input clk); 
reg[7:0] tempa,tempb; 
reg tempci,firstco,secondco,thirdco; 
    reg[1:0] firsts,thirda,thirdb; 

    reg[3:0] seconda,secondb,seconds; 

    reg[5:0] firsta,firstb,thirds; 

    always @(posedge clk) 

         begin 

         tempa=ina;  tempb=inb;  tempci=cin;          
         end 

    always @(posedge clk) 

         begin 

         {firstco,firsts}=tempa[1:0]+tempb[1:0]+tempci; 

                                              //第一级加（低2位） 

         firsta=tempa[7:2];                   //未参加计算的数据缓存 

         firstb=tempb[7:2]; 

         end 

    always @(posedge clk) 

         begin 

         {secondco,seconds}={firsta[1:0]+firstb[1:0]+firstco,firsts}; 

                                         //第二级加（第2、3位相加） 

         seconda=firsta[5:2];                     //4-7位数据缓存 

         secondb=firstb[5:2]; 

         end 

    always @(posedge clk) 

         begin 

         {thirdco,thirds}={seconda[1:0]+secondb[1:0]+secondco,seconds}; 

                                         //第三级加（第 4、5位相加） 

         thirda=seconda[3:2];            //6，7位数据缓存 

         thirdb=secondb[3:2]; 

         end 

    always @(posedge clk) 

         begin 

         {cout,sum}={thirda[1:0]+thirdb[1:0]+thirdco,thirds}; 

                                         //第四级加（高两位相加） 

         end 

    endmodule