题目:编写Verilog代码描述跨时钟域信号传输,慢时钟域到快时钟域 reg [1:0] signal_r; always @(posedge clk or negedge rst_n)begin if(rst_n == 1'b0)begin signal_r <= 2'b00; end else begin signal_r <= {signal_r[0], signal_in}; end end assign signal_out = signal_r[1];