-----边沿检测

//边沿检测

检测上升沿与下降沿

module edege(
	input				clk,
	input				rst_n,
	input				signal,
	output			neg_edeg,
	output			pos_edge
);

reg signal_r;
always@(posedge clk or negedge rst_n )
	if(!rst_n)
		signal_r<=0;
	else
		signal_r<=signal;
		
assign pos_edge=signal & (!signal_r);
assign neg_edeg=(!signal )& (signal_r);

endmodule

 

`timescale 1ns/1ns
module edege_tb();
reg      clk;
reg      rst_n;
reg      signal;
wire     neg_edeg;
wire     pos_edge;

initial begin
	clk=0;
	rst_n=0;
	signal=0;
	#100.2;
	rst_n=1;
	#100;
	signal=1;
	#200;
	signal=0;
	#300;
	$stop;
end

always #10 clk=~clk;



edege  edege(
	.clk(clk),
	.rst_n(rst_n),
	.signal(signal),
	.neg_edeg(neg_edeg),
	.pos_edge(pos_edge)
);


endmodule