https://hdlbits.01xz.net/wiki/Fsm_ps2data
module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done); //
// FSM from fsm_ps2
parameter S0 =0,S1=1,S2=2,S3=3;
reg [1:0] state , next;
reg [23:0]d;
// State transition logic (combinational)
always @(*)
begin
case (state)
S0: next = (in[3] == 1)? S1:S0;
S1: next =S2;
S2: next =S3;
S3: next = (in[3] == 1)? S1:S0;
endcase
end
// State flip-flops (sequential)
always @(posedge clk)
begin
if (reset)
begin
state <= S0;
d<=24'b0;
end
else
begin
state <= next;
d<={d[15:0],in};
end
end
// Output logic
assign done = (state == S3);
assign out_bytes = d;
// New: Datapath to store incoming bytes.
endmodule