HDLBits—Fsm ps2data

现在，有了一个状态机，它将识别 PS/2 字节流中的三字节消息，请添加一个数据路径，该数据路径还将在收到数据包时输出 24 位（3 字节）消息（out_bytes[23：16] 是第一个字节，out_bytes[15：8] 是第二个字节，依此类推）。

每当断言完成信号时，out_bytes都需要有效。您可以在其他时间输出任何内容（即，不要在乎）。

错误写法：

状态1中的out_bytes赋值存在只在if或者else中赋值的情况，导致结果错误。且由于无法实现都在if、else中赋值可以考虑在时序逻辑中进行赋值，可以只在if或者else中赋值

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //

    // FSM from fsm_ps2
module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //
    reg[1:0] state,next_state;
    reg[7:0] last_in;
    integer count;
    always@(*)begin
        case(state)
            0:begin
                done = 0;
                if(in[3])begin
                   next_state = 1; 
                end
                else begin
                   next_state = 0; 
                end
            end
            1:begin
                done = 0;
                if(count==2)begin
                   next_state = 2;
                   out_bytes[15:8] = last_in;
                end
                else begin
                    out_bytes[23:16] = last_in;
                    next_state = 1; 
                end
            end
            2:begin
                done = 1;
                out_bytes[7:0] = last_in;
                if(in[3])begin
                   next_state = 1;
                end
                else begin
                   next_state = 0;
                end
            end
        endcase
    end
    always@(posedge clk)begin
        if(reset)begin
           state<=0; 
           last_in<=0;
        end
        else begin
            last_in<=in;
            if(next_state==1)begin
               count<=count+1; 
            end
            else begin
               count<=0; 
            end
            state<=next_state;
        end
    end
    // FSM from fsm_ps2

    // New: Datapath to store incoming bytes.

endmodule

    // New: Datapath to store incoming bytes.

endmodule

正确代码： 

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //
    reg[1:0] state,next_state;
    integer count;
    always@(*)begin
        case(state)
            0:begin
                done = 0;
                if(in[3])begin
                   next_state = 1; 
                end
                else begin
                   next_state = 0; 
                end
            end
            1:begin
                done = 0;
                if(count==2)begin
                   next_state = 2;
                end
                else begin
                    next_state = 1; 
                end
            end
            2:begin
                done = 1;
                if(in[3])begin
                   next_state = 1;
                end
                else begin
                   next_state = 0;
                end
            end
        endcase
    end
    always@(posedge clk)begin
        if(reset)begin
           state<=0; 
        end
        else begin
            if(next_state==1&count==1)begin
                out_bytes[15:8] <= in;
            end
            if(next_state==1&count==0)begin
                out_bytes[23:16] <= in;
            end
            if(next_state==2)begin
                out_bytes[7:0] <= in;
            end
            if(next_state==1)begin
               count<=count+1; 
            end
            else begin
               count<=0; 
            end
            state<=next_state;
        end
    end
    // FSM from fsm_ps2

    // New: Datapath to store incoming bytes.

endmodule