Mearly状态机时序检测设计
139.Exams/ece241 2013 q8(Q8:Design a Mealy FSM)
原题:Implement a Mealy-type finite state machine that recognizes the sequence “101” on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the “101” sequence is detected. Your FSM should also have an active-low asynchronous reset. You may only have 3 states in your state machine. Your FSM should recognize overlapping sequences.
简单说明:设计Mealy状态机,检测‘101’时序;输入信号:x;输出信号:z
链接:https://hdlbits.01xz.net/wiki/Exams/ece241_2013_q8
Mealy状态转换图:
注意:Mealy状态机的输出是现态和输入的函数
aresetn:异步复位,低电平有效
module top_module (
input clk,
input aresetn, // Asynchronous active-low reset
input x,
output z );
reg [2:0