Fsm serialdata

module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //

// Use FSM from Fsm_serial
parameter idle=0,start=1,data1=2,data2=3,data3=4,data4=5,
data5=6,data6=7,data7=8,data8=9,stop=10,error=11;
reg [3:0]c_s,n_s;
always @(posedge clk)
    begin
        if(reset)
            c_s<=idle;
        else
            c_s<=n_s;
    end
always @(*)
    begin
        if(~reset)
            begin
        case(c_s)
        	idle:n_s=~in?start:idle;
            start:n_s=data1;
            data1:n_s=data2;
            data2:n_s=data3;
            data3:n_s=data4;
            data4:n_s=data5;
            data5:n_s=data6;
            data6:n_s=data7;
            data7:n_s=data8;
            data8:n_s=in?stop:error;
            error:n_s=in?idle:error;
            stop:n_s=in?idle:start;
            default:n_s=idle;
        endcase
            end
        else
            n_s=idle;
    end
assign done=(c_s==stop);
// New: Datapath to latch input bits.
reg [7:0]data;
always @(posedge clk)
    if(reset)
        data<=0;
	else
    begin
        case(c_s)
            start:data[0]=in;
            data1:data[1]=in;
            data2:data[2]=in;
            data3:data[3]=in;
            data4:data[4]=in;
            data5:data[5]=in;
            data6:data[6]=in;
            data7:data[7]=in;
        endcase
    end
assign out_byte=data;

endmodule