Verilog task任务使用注意点

有关Verilog 的task用法，在此不再赘述，这此只提需要注意的地方。
一、两种调用task输出情形：
如何在task里面有输出，那么输出到外部寄存器是有两个时钟延时的，但如果task中没有输出，直接调用task外的寄存器的话，寄存器在下个时钟便会更改。下面举例子说明：
1、带有延时
当调用transfer时寄存器的bai、shi和ge存在两个时钟的延时。

//
reg[7:0] bai;
reg[7:0] shi;
reg[7:0] bai;
always @(posedge clk)
begin
		transfer(8'd120,bai,shi,ge);
end

task transfer;
input  [7:0] num;
output [7:0] bit_bai,bit_shi,bit_ge;
begin
      if(num >= 8'd100)
      begin
            bit_bai <= (num[3:0] + num[7:4]*16)/100;
            bit_shi <= ((num[3:0] + num[7:4]*16)/10)%10;
            bit_ge  <= (num[3:0] + num[7:4]*16)%10;
      end
      else if(num < 8'd100 && num >= 8'd10)
      begin
            bit_bai <= 8'h27;
            bit_shi <= (num[3:0] + num[7:4]*16)/10;
            bit_ge  <= (num[3:0] + num[7:4]*16)%10;
      end
      else
      begin
            bit_bai <= 8'h27;
            bit_shi <= 8'h27;
            bit_ge  <= num[3:0] + num[7:4]*16;
      end
end 
endtask

2、不带延时
当调用transfer时寄存器的bit_bai、bit_shi和bit_ge存在一个时钟的延时，即下一个时钟变化。

//
reg[7:0] bit_bai;
reg[7:0] bit_shi;
reg[7:0] bit_ge;
always @(posedge clk)
begin
		transfer(8'd120);
end

task transfer;
input  [7:0] num;
begin
      if(num >= 8'd100)
      begin
            bit_bai <= (num[3:0] + num[7:4]*16)/100;
            bit_shi <= ((num[3:0] + num[7:4]*16)/10)%10;
            bit_ge  <= (num[3:0] + num[7:4]*16)%10;
      end
      else if(num < 8'd100 && num >= 8'd10)
      begin
            bit_bai <= 8'h27;
            bit_shi <= (num[3:0] + num[7:4]*16)/10;
            bit_ge  <= (num[3:0] + num[7:4]*16)%10;
      end
      else
      begin
            bit_bai <= 8'h27;
            bit_shi <= 8'h27;
            bit_ge  <= num[3:0] + num[7:4]*16;
      end
end 
endtask
/

二、不能在task中定义寄存器reg，不然这个寄存器不工作。