verible (verible-verilog-format)

Verible 是一套 SystemVerilog / verilog 开发工具，包括解析器、样式检查器、格式化程序和语言服务器。这里为主要分享关于格式化工具verible-verilog-format的使用。用来格式化verilog代码，实现代码风格统一。
python3 format_verilog.py -i filelist.f

import os
import argparse

# if you want to modify the format parameter, you can change it below.
# the details of parameter reference: https://chipsalliance.github.io/verible/verilog_format.html
format_parameter = '--column_limit=200 --indentation_spaces=2'

parser = argparse.ArgumentParser(description='format verilog by verible')
parser.add_argument('--input', '-i', help='input filelist(.f) file', required=True)
args = parser.parse_args()

with open(args.input, mode="r") as filelist:
    filepaths = filelist.readlines()
    for filepath in filepaths:
        if(filepath):
            # print("./verible-verilog-format --inplace {0} {1}".format(format_parameter,filepath))
            os.popen("./verible-verilog-format --inplace {0} {1}".format(format_parameter,filepath))
                               
filelist.close()
print("format verilog done")

verible 项目托管于github，项目地址：https://github.com/chipsalliance/verible

重要 option --inplace --wrap_end_else_clauses
也有vscode插件

--column_limit=300 --indentation_spaces=2 --assignment_statement_alignment=align --named_port_alignment=align - -port_declarations_alignment=align --module_net_variable_alignment=align

https://www.youtube.com/watch?v=xLxNHBzmGiI