vivado怎么解决Unconstrained Logical Port [DRC UCIO-1] 错误

最新推荐文章于 2024-07-19 10:33:09 发布

老板拿瓶阔落

最新推荐文章于 2024-07-19 10:33:09 发布

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分类专栏： vivado 文章标签： fpga

本文链接：https://blog.csdn.net/weixin_44495643/article/details/106941778

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在Vivado中遇到[DRC UCIO-1]错误，提示3个逻辑端口没有指定位置约束。错误可能导致I/O冲突或与板级电源或连接性不兼容。解决方法包括确保所有端口都有LOC约束，或者在不推荐的情况下，通过设置警告级别来允许位流生成。问题端口为rx_sht20, rx_ch2o和rx_adc。按照网上的解决方案操作无效，问题在于xdc约束文件中注释和约束在同一行，修正此问题后，错误得以解决。" 129374991,8651756,快速构建图像分割模型：Segmentation Models库教程,"['深度学习', '神经网络', '图像处理']

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Vivado生成比特流报错：

[DRC UCIO-1] Unconstrained Logical Port:3 out of 139 logical ports have no user assigned specific location constraint (LOC).

error信息

报错信息如下：[DRC UCIO-1] Unconstrained Logical Port: 3 out of 139 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add thi