1 遇到问题
使用vivado2019.1软件,生成bit文件时报错;提示如下:
[DRC UCIO-1] Unconstrained Logical Port: 2 out of 29 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: pci_exp_txn, and pci_exp_txp.
2 解决方法
按照提示添加约束语句即可,在XDC文件中添加如下约束即可解决。
约束为:set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
3 结束语
希望对你有帮助,如果遇到问题,可以一起沟通讨论,邮箱:jhqwy888@163.com。