异步跨时钟域握手处理（Verilog）

RTL代码：

module req_ack(
	input clk_a,
	input rst_n,
	input pulse_a,
	input clk_b,
	output pulse_b
);
	reg req;		//请求信号
	reg [2:0]req_b;
	reg ack;		//应答信号
	reg [2:0]ack_a;
	
	always@(posedge clk_a or negedge rst_n)begin
		if(!rst_n)
			req <= 1'b0;
		else if(pulse_a)
			req <= 1'b1;
		else if(~ack_a[2] & ack_a[1])
			req <= 1'b0;
		else
			req <= req;
	end
	
	//时钟域b同步时钟域a的req信号
	always@(posedge clk_b or negedge rst_n)begin
		if(!rst_n)
			req_b <= 'd0;
		else
			req_b <= {req_b[1:0],req};
	end 
	
	always@(posedge clk_b or negedge rst_n)begin
		if(!rst_n)
			ack <= 1'b0;
		else if(~req_b[2] & req_b[1])
			ack <= 1'b1;
		else if(~req_b[1] & req_b[2])
			ack <= 1'b0;
		else 
			ack <= ack;
	end 
	
	//时钟域a同步时钟域b的ack信号
	always@(posedge clk_a or negedge rst_n)begin
		if(!rst_n)
			ack_a <= 'd0;
		else
			ack_a <= {ack_a[1:0],ack};
	end
	
	assign pulse_b = req_b[1] & (~req_b[2]);
	

endmodule

仿真代码：

`timescale 1ns/1ns
module req_ack_tb;
    
    reg clk_a;
    reg clk_b;
    reg pulse_a;
    reg rst_n;
    wire pulse_b;
    
    req_ack req_ack_inst(
	   .clk_a      (clk_a),
	   .rst_n      (rst_n),
	   .pulse_a    (pulse_a),
       .clk_b      (clk_b),
	   .pulse_b    (pulse_b)
);
    
    initial clk_a = 0;
    always#10 clk_a = ~clk_a;
    
    initial clk_b = 0;
    always#50 clk_b = ~clk_b;
    
    initial begin
        rst_n = 0;
        pulse_a = 0;
        #200;
        rst_n = 1;
        #200;
        pulse_a = 1;
        #20;
        pulse_a = 0;
        #5000;
    end
    
endmodule

仿真波形：