module Carry_Lookahead_Adder (A, B, Cin, Sum, Cout);
input [3:0] A, B;
input Cin;
output [3:0] Sum;
output Cout;
assign G0 = A[0] & B[0];
assign P0 = A[0] ^ B[0];
assign G1 = A[1] & B[1];
assign P1 = A[1] ^ B[1];
assign G2 = A[2] & B[2];
assign P2 = A[2] ^ B[2];
assign G3 = A[3] & B[3];
assign P3 = A[3] ^ B[3];
assign C1 = G0 | (P0 & Cin);
assign C2 = G1 | (P1 & C1);
assign C3 = G2 | (P2 & C2);
assign Cout = G3 | (P3 & C3);
assign Sum = A + B + Cin;
endmodule
Verilog HDL 基本电路设计6:超前进位加法器
于 2023-03-17 12:40:37 首次发布