细节就不说了,直接上代码
module design2(
input clk,
input din,
input dstate_in,
output reg dout =0,
output reg dstate = 0//为1的时候是发送数据,其余时候是帧头或者帧尾
);
always@(posedge clk)begin
dout<=din;
dstate<=dstate_in;
end
endmodule
测试文件
`timescale 1ns / 1ps
module tb3;
reg clk;
wire dout;
reg [1-1:0]din=0;
reg [1-1:0]DataMem[0:8000-1];
reg [13-1:0] AddrMem = 13'd0;//8064
reg [32-1:0] frame_head = 32'h1ACFFC1D;//帧头32位
reg [1-1:0] dstate_in = 1'b0;
design2 nnnnnnnnnnnnnnnnname(
.clk(clk),
.dout(dout),
.din(din),
.dstate(dstate),
.dstate_in(dstate_in)
);
integer dout_file1;
initial begin
clk = 0;
$readmemh("../../../../SimData/CSV/FrmBin.txt", DataMem);
dout_file1=$fopen("../../../../SimData/CSV/myFrmBin.txt"); //打开所创建的文件
if(dout_file1 == 0)begin
$display ("can not open the file!"); //创建文件失败,显示can not open the file!
$stop;
end
end
always #1 clk = ~clk;
always @(posedge clk)begin
if(AddrMem<'d32)begin
din<=frame_head[31-AddrMem];//不是32减去索引
AddrMem<=AddrMem+1;
dstate_in<=0;
end
else if(AddrMem<=8000+32)
begin
din<=DataMem[AddrMem-32];
AddrMem<=AddrMem+1;
dstate_in<=1;
if(AddrMem==8000+32)
begin
AddrMem <= 0;
end
end
end
always @(posedge clk)
begin
$fdisplay(dout_file1,"%d",dout); //保存有符号数据
end
endmodule