Verilog状态机Moore 与Mearly

Moore型状态机：下一状态只由当前状态决定，即次态=f(现状，输入)，输出=f（现状）；
Mealy型状态机：下一状态不但与当前状态有关，还与当前输入值有关，即次态=f(现状，输入)，输出=f（现状，输入）；
下面从一个序列检测110举例：

module SquDetor (
                input     clk,
                input     rst,
                input     din,
                output reg   dout_ML,
                output reg   dout_MR
);
//------------Moore
parameter MR_IDLE = 2'b00;
parameter MR_S1 = 2'b01;
parameter MR_S2 = 2'b10;
parameter MR_S3 = 2'b11;

reg [1:0] next_state_ml,curr_state_ml;
reg [1:0] next_state_mr,curr_state_mr;

always@(posedge clk or negedge rst) begin
  if (!rst) 
    curr_state_mr <= MR_IDLE;
  else 
    curr_state_mr <= next_state_mr;
end

always@(clk or din) begin
  next_state_mr = MR_IDLE;
  case(curr_state_mr) 
    MR_IDLE: next_state_mr = (din==1)? MR_S1: MR_IDLE;
    MR_S1: next_state_mr = (din==1)? MR_S2: MR_IDLE;
    MR_S2: next_state_mr = (din==1)? MR_S2: MR_S3;
    MR_S3: next_state_mr = (din==1)? MR_S1: MR_IDLE;
    default: next_state_mr  <= MR_IDLE;
  endcase
end  

always@(posedge clk or negedge rst) begin
 if (!rst) 
   dout_MR <= 1'b0;
 else if(curr_state_mr == MR_S3)
   dout_MR <= 1'b1;
 else 
   dout_MR <= 1'b0;
 end
//------------------------Mearly
parameter ML_IDLE = 2'b00;
parameter ML_S1 = 2'b01;
parameter ML_S2 = 2'b10;

always@(posedge clk or negedge rst) begin
  if (!rst) 
    curr_state_ml <= ML_IDLE;
  else 
    curr_state_ml <= next_state_ml;
end

always@(clk or din) begin
  case(curr_state_ml) 
    ML_IDLE: next_state_ml = (din==1)? ML_S1 : ML_IDLE;
    ML_S1:   next_state_ml = (din==1)? ML_S2 : ML_IDLE;
    ML_S2:   next_state_ml = (din==1)? ML_S2 : ML_IDLE;
    default: next_state_ml  <= ML_IDLE;
  endcase
end  

always@(posedge clk or negedge rst) begin
 if (!rst) 
   dout_ML <= 1'b0;
 else if(curr_state_ml == ML_S2 && din == 0)
   dout_ML <= 1'b1;
 else 
   dout_ML <= 1'b0;
 end
endmodule

• 测试

- module test();
reg clk;
reg rst;
reg din;
wire dout_MR;
wire dout_ML;

SquDetor u1(
          .clk(clk),
          .rst(rst),
          .din(din),
          .dout_ML(dout_ML),          
          .dout_MR(dout_MR)          
          );
initial begin
  rst = 1;
  #20 rst = 0;
  #40 rst = 1;
end

parameter period = 20;
initial begin
  clk = 0;
  forever #(period/2) clk = ~clk;
end

initial begin
  din = 0;
  #50
  #period din = 1;
  #period din = 0;
  #period din = 1;
  #period din = 0;
  #period din = 0;
  #period din = 1;
  #period din = 1;
  #period din = 0;
  #period din = 1;
  #period din = 1;
  #period din = 1;
  #period din = 1;
  #period din = 1;
  #period din = 1;
  #period din = 0;
  #100 $finish;
end

initial begin
  $fsdbDumpfile("SquDetor.fsdb");
  $fsdbDumpvars;
 end
 endmodule

• 仿真结果
  
• 总结：
• Moore机比Mearly晚一拍输出
• Mearly机的状态通常比Moore少
• Mealy机的Moore的三段式状态机区别
  （1）：状态的不同
  （2）：第三段状态机:
  Moore：if(curr_state_ml == ML_S3) 只与当前状态有关
  Mearly: if(curr_state_ml == ML_S2 && din == 0) 与当前状态和输入有关