Verilog刷题HDLBits——Adder3

题目描述

Now that you know how to build a full adder, make 3 instances of it to create a 3-bit binary ripple-carry adder. The adder adds two 3-bit numbers and a carry-in to produce a 3-bit sum and carry out. To encourage you to actually instantiate full adders, also output the carry-out from each full adder in the ripple-carry adder. cout[2] is the final carry-out from the last full adder, and is the carry-out you usually see.

代码

// 解法一
module top_module( 
    input [2:0] a, b,
    input cin,
    output [2:0] cout,
    output [2:0] sum );
    
    wire cc0,cc1,cc2;
    full_adder fadd1(a[0],b[0],cin,cc0,sum[0]);
    full_adder fadd2(a[1],b[1],cc0,cc1,sum[1]);
    full_adder fadd3(a[2],b[2],cc1,cc2,sum[2]);
    
    assign cout = {cc2,cc1,cc0};

endmodule

module full_adder(input a,b,cin,output cout,sum);
    assign cout = a&b|a&cin|b&cin;
    assign sum = a^b^cin;
endmodule

// 解法二
module top_module( 
    input [2:0] a, b,
    input cin,
    output [2:0] cout,
    output [2:0] sum );
    
    fadd inst1 (a[0], b[0], cin, cout[0], sum[0]);
    fadd inst2 (a[1], b[1], cout[0], cout[1], sum[1]);
    fadd inst3 (a[2], b[2], cout[1], cout[2], sum[2]);

endmodule


module fadd( 
    input a, b, cin,
    output cout, sum );
    
    assign {cout, sum} = a + b + cin;

endmodule

结果