Verilog刷题HDLBits——Count10

题目描述

Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0.

代码

// 我的解法
module top_module (
    input clk,
    input reset,        // Synchronous active-high reset
    output [3:0] q);
    
    always@(posedge clk)
        begin
            if(reset)
                q<=4'h0;
            else
                begin
                    if(q==4'd9)
                        q<=4'h0;
                    else
                        q<=q+1;
                end
        end

endmodule

// 参考解法
module top_module(
	input clk,
	input reset,
	output reg [3:0] q);
	
	always @(posedge clk)
		if (reset || q == 9)	// Count to 10 requires rolling over 9->0 instead of the more natural 15->0
			q <= 0;
		else
			q <= q+1;
	
endmodule

结果