HDLBits练习——Count10

Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0.

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前言

两个输入，包括一个时钟clk，一个高电平有效的同步置位信号reset；一个输出信号q。

代码

module top_module (
    input clk,
    input reset,       
    output [3:0] q);
    always@(posedge clk)begin
        if(reset) q<=4'd0;
        else if(q<4'd9) q<=q+1'b1;
        else q<=4'd0;
    end
endmodule

总结

计数范围小于实际计值范围，即在if的循环内添加一个else if条件即可。