HDLbits--count10

错误：
输出为0-a

原因：
count<10;

解决方法：
count<9;

module top_module (
    input clk,
    input reset,        // Synchronous active-high reset
    output [3:0] q);
    
    reg [3:0] count;
    initial 
        count  =0;
    
    always @(posedge clk)
        begin
            if(reset)
                count<=0;
            else if(count<4'b1001)
                count <=count+'b1;
            else 
                count <=0;
        end
    assign q = count;

endmodule