Verilog刷题HDLBits——Fsm1

不会敲代码的研究生不是好空管

已于 2022-12-18 19:30:07 修改

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文章标签： fpga开发

于 2022-12-18 19:29:01 首次发布

本文链接：https://blog.csdn.net/weixin_45968042/article/details/128365066

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这篇博客介绍了如何使用Verilog实现一个具有两个状态、一个输入和一个输出的Moore状态机，包括同步和异步复位的情况。作者提供了两种不同的解法，一种是将状态转换逻辑、状态寄存器更新和输出逻辑分开实现，另一种则是更简洁的编码方式。参考解法中，博主强调了有限状态机的三个主要部分：状态转换逻辑、DFF（边沿触发DFF）和输出逻辑，并展示了如何用阻塞赋值进行组合逻辑和边沿触发的时序逻辑编程。

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题目描述

This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.

This exercise is the same as fsm1s, but using asynchronous reset.
在这里插入图片描述

代码

// 我的解法
module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;

    always @(*) begin    // This is a combinational always block
        // State transition logic
        case(state)
            A: if(in==0)
                next_state<=B;
            	else
                    next_state<=A;
            B:if(in==0)
                next_state<=A;
            	else
                    next_state<=B;
            default: next_state<=B;
        endcase
    end

    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        // State flip-flops with asynchronous reset
        if(areset)
            state<=B;
        else
            state<=next_state;
    end

    // Output logic
    // assign out = (state == ...);
    assign out = state;

endmodule


// 参考解法
module top_module (
	input clk,
	input in,
	input areset,
	output out
);

	// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
	// It doesn't really matter what assignment is used, as long as they're unique.
	parameter A=0, B=1;
	reg state;		// Ensure state and next are big enough to hold the state encoding.
	reg next;
    
    
    // A finite state machine is usually coded in three parts:
    //   State transition logic
    //   State flip-flops
    //   Output logic
    // It is sometimes possible to combine one or more of these blobs of code
    // together, but be careful: Some blobs are combinational circuits, while some
    // are clocked (DFFs).
    
    
    // Combinational always block for state transition logic. Given the current state and inputs,
    // what should be next state be?
    // Combinational always block: Use blocking assignments.
    always@(*) begin
		case (state)
			A: next = in ? A : B;
			B: next = in ? B : A;
		endcase
    end
    
    
    
    // Edge-triggered always block (DFFs) for state flip-flops. Asynchronous reset.
    always @(posedge clk, posedge areset) begin
		if (areset) state <= B;		// Reset to state B
        else state <= next;			// Otherwise, cause the state to transition
	end
		
		
		
	// Combinational output logic. In this problem, an assign statement is the simplest.
	// In more complex circuits, a combinational always block may be more suitable.
	assign out = (state==B);

	
endmodule