Verilog刷题[hdlbits] ：Conditional

题目：Conditional

Verilog has a ternary conditional operator ( ? : ) much like C:

(condition ? if_true : if_false)

This can be used to choose one of two values based on condition (a mux!) on one line, without using an if-then inside a combinational always block.

Examples:

(0 ? 3 : 5) // This is 5 because the condition is false.
(sel ? b : a) // A 2-to-1 multiplexer between a and b selected by sel.

always @(posedge clk) // A T-flip-flop.
q <= toggle ? ~q : q;

always @(*) // State transition logic for a one-input FSM
case (state)
A: next = w ? B : A;
B: next = w ? A : B;
endcase

assign out = ena ? q : 1’bz; // A tri-state buffer

((sel[1:0] == 2’h0) ? a : // A 3-to-1 mux
(sel[1:0] == 2’h1) ? b :
c )

A Bit of Practice

练习

Given four unsigned numbers, find the minimum. Unsigned numbers can be compared with standard comparison operators (a < b). Use the conditional operator to make two-way min circuits, then compose a few of them to create a 4-way min circuit. You’ll probably want some wire vectors for the intermediate results.

• 给定四个无符号数，求最小值。无符号数可以与标准比较运算符(a < b)进行比较。使用条件运算符制作双向最小电路，然后将其中的几个组成一个4路最小电路。你可能需要一些线向量作为中间结果。

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);//

    // assign intermediate_result1 = compare? true: false;
    wire [7:0] com1;
	wire [7:0] com2;
    wire [7:0] com3;
    
    assign com1 = a < b ? a : b;
    assign com2 = com1 < c ? com1 : c;
    assign com3 = com2 < d ? com2 : d;

    assign min =  com3;
    
endmodule