对于快时钟采样慢时钟,往往采用打两拍+边沿检测的方法。代码如下:
module (
input fast_clk,
input slow_clk,
input rst_n,
input slow_pulse,
output fast_pulse
);
reg pulse_reg,pulse_reg_r1,pulse_reg_r2;
always@(posedge fast_clk or negedge rst_n)begin
if(!rst_n)begin
pulse_reg <= 0;
pulse_reg_r1 <= 0;
pulse_reg_r2 <= 0;
end
else begin
pulse_reg <= slow_pulse;
pulse_reg_r1 <= pulse_reg;
pulse_reg_r2 <= pulse_reg_r1;
end
end
assign fast_pulse = (~pulse_reg_r2 )&pulse_reg_r1;
endmodule
对于慢时钟采样快时钟,为了避免快信号已经变化,而慢时钟没有采样到的问题,通过将快信号进行【信号展宽】+【握手】的方式,在慢时钟上进行采样。代码如下:
module slow_fast(
input slow_clk,
input fast_clk,
input fast_pulse,
input rst_n
output slow_pulse
);
reg fast_req;
wire slow_ack;
reg slow_reg,slow_reg_r1,slow_reg_r2;
reg slow_ack_reg,slow_ack_reg_r1;
//信号展宽fast_req
always@(posedge fast_clk or negedge rst_n)begin
if(!rst_n)
fast_req <= 0;
else if(fast_pulse = 1)
fast_req <= 1;
else if(slow_ack = 1)
fast_req <= 0;
else
fast_req <= fast_req;
end
//slow_pulse生成
always@(posedge slow_clk or nengedge rst_n)begin
if(!rst_n)begin
slow_reg <= 0;
slow_reg_r1 <= 0;
slow_reg_r2 <= 0;
end else begin
slow_reg <= fast_req;
slow_reg_r1 <= slow_reg;
slow_reg_r2 <= slow_reg_r1;
end
end
//返回slow_ack,进行两次打拍子
always@(posedge slow_clk or nengedge rst_n)begin
if(!rst_n)begin
slow_ack_reg <= 0;
slow_ack_reg_r1 <= 0;
end else begin
slow_ack_reg <= slow_reg_r1;
slow_ack_reg_r1 <= slow_ack_reg;
end
end
assign slow_ack = slow_ack_reg_r1;
assign slow_pulse = (~slow_reg_r2)&&slow_reg_r1;
endmodule
注意这种情况仅适用于单bit的跨时钟域传输,对于多bit跨时钟域传输应该使用FIFO会比较好