verilog实现4bit超前进位加法器

电路的结构图如图

module adder4bit_loodahead_carry(
input    [3:0]    a,
input    [3:0]    b,
input             c_in,
output    [3:0]   y,
output            cout    

output     [3:0]  Pm,
output     [3:0]  Gm
);

wire [4:1] c_wire;
wire [3:0] P,G;

adder1bit a1(a[0],b[0],c_cin,y[0],P[0],G[0]);
adder1bit a2(a[1],b[1],c_wire[1],y[1],P[1],G[1]);
adder1bit a3(a[2],b[2],c_wire[2],y[2],P[2],G[2]);
adder1bit a4(a[3],b[3],c_wire[3],y[3],P[3],G[4]);

adder4bit_cla(P,G,c_in,c_wire,Pm,Gm);

assign cout = c_wire[4];
endmodule

module adder1bit(
input       a,
input       b,
input       c_in,
output      y,
output      g,
output      p   
);


assign y = a ^ b ^ c_in;
assign g = a & b;
assign p = a | b;

endmodule



module 4_cla(
input    [3:0]    p,
input    [3:0]    g,
input             c_in,
output    [4:1]   C_IN;
output            Pm;
o