目录
1\ KMAP1
Implement the circuit described by the Karnaugh map below.
Try to simplify the k-map before coding it. Try both product-of-sums and sum-of-products forms. We can't check whether you have the optimal simplification of the k-map. But we can check if your reduction is equivalent, and we can check whether you can translate a k-map into a circuit.
CORRECT:
module top_module(
input a,
input b,
input c,
output out );
assign out=a|b|c; //只有ABC同时为0时才不成立，反过来的话就是有一个是1就成立。
endmodule
2\ Kmap2
Implement the circuit described by the Karnaugh map below.
Try to simplify the k-map before coding it. Try both product-of-sums and sum-of-products forms. We can't check whether you have the optimal simplification of the k-map. But we can check if your reduction is equivalent, and we can check whether you can translate a k-map into a circuit.
画卡诺图的时候注意，圈中的元素个数必须是二的幂次方。
CORRECT1:
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out=a&(!b)&d | b&c&d | (!a) & (!d) | (!b) & (!c);
endmodule
CORRECT2:
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = ~a & ~d | ~b & ~c | b & c & d | a & c & d;
endmodule
3\ Kmap3
Implement the circuit described by the Karnaugh map below.
Try to simplify the k-map before coding it. Try both product-of-sums and sum-of-products forms. We can't check whether you have the optimal simplification of the k-map. But we can check if your reduction is equivalent, and we can check whether you can translate a k-map into a circuit.
这里的d既可以当1也可以当0用。
因此画法为：
CORRECT1:
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out=a|(~a&~b&c);
endmodule
CORRECT2:
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out=a|(!a&!b&c);
endmodule
ERRO:
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out=a+(~a&~b&c);
endmodule
4\ Kmap4
Implement the circuit described by the Karnaugh map below.
Try to simplify the k-map before coding it. Try both product-of-sums and sum-of-products forms. We can't check whether you have the optimal simplification of the k-map. But we can check if your reduction is equivalent, and we can check whether you can translate a k-map into a circuit.
HINT:
For this function, changing the value of any one input always inverts the output. It is a simple logic function, but one that can't be easily expressed as SOP nor POS forms.
本题没法通过画卡诺图去化简，只能把每一个1都挑出来然后合并：
y=a'bc'd+ab'c'd'+a'b'c'd+abc'd+a'bcd+ab'cd+a'b'cd'+abcd'
=(a'b+ab')c'd'+(a'b'+ab)c'd+(a'b+ab')cd+(a'b'+ab)cd'
=(a'b+ab')(c'd'+cd)+(a'b'+ab)(c'd+cd')
=(a^b)&!(c^d)|!(a^b)&(c^d)
CORRECT:
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out=(a^b)&!(c^d)|!(a^b)&(c^d);
endmodule
5\ Exams/ece241 2013 q2
A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this system. For example, 7 corresponds to a,b,c,d being set to 0,1,1,1, respectively.(具有四个输入(A,b,c,d)的单输出数字系统在输入上出现2、7或15时生成逻辑1，在输入上出现0、1、4、5、6、9、10、13或14时生成逻辑0。数字3、8、11和12的输入条件在这个系统中从未出现过。例如，7对应a、b、c、d分别设为0、1、1、1。)
Determine the output out_sop in minimum SOP form, and the output out_pos in minimum POS form.(确定输出out_sop为最小SOP形式也就是乘积和，输出out_pos为最小POS形式，也就是和之积。)
HINT:
先自己画卡诺图：
先画SOP式子表示的部分，蓝圈所示；
再画POS式子表示的部分，绿圈所示：(记得将原式子反向计算，也就是把加变成乘，把非反向)
然后就可以编代码了。
CORRECT:
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = c & d | ~a & ~b & c;
assign out_pos = ~((~c | ~d) & (a | b | ~c));
endmodule
6\ Exams/m2014 q3
Consider the function f shown in the Karnaugh map below.
Implement this function. d is don't-care, which means you may choose to output whatever value is convenient.
HINT:
CORRECT:
module top_module (
input [4:1] x,
output f );
assign f=!x[1]&x[3]|x[2]&x[4];
endmodule
7\ Exams/2012 q1g
Consider the function f shown in the Karnaugh map below. Implement this function.
(The original exam question asked for simplified SOP and POS forms of the function.)
HINT:
CORRECT:
module top_module (
input [4:1] x,
output f
);
assign f=!x[2]&!x[3]&!x[4]|x[1]&!x[2]&!x[4]|x[2]&x[3]&x[4]|!x[1]&x[3];
endmodule
8\ Exams/ece241 2014 q3
For the following Karnaugh map, give the circuit implementation using one 4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using as few as possible. You are not allowed to use any other logic gate and you must use a and b as the multiplexer selector inputs, as shown on the 4-to-1 multiplexer below.(对于下面的Karnaugh映射，给出使用一个4对1复用器和尽可能多的2对1复用器的电路实现，但尽可能少地使用。你不允许使用任何其他逻辑门，你必须使用a和b作为多路复用器选择器输入，如下面的4比1多路复用器所示。)
You are implementing just the portion labelled top_module, such that the entire circuit (including the 4-to-1 mux) implements the K-map.(您只实现了标记为top_module的部分，这样整个电路(包括4比1的mux)实现了k映射。)
(The requirement to use only 2-to-1 multiplexers exists because the original exam question also wanted to test logic function simplification using K-maps and how to synthesize logic functions using only multiplexers. If you wish to treat this as purely a Verilog exercise, you may ignore this constraint and write the module any way you wish.)((只使用2对1多路复用器的要求存在，因为最初的考试题目还想测试使用k映射简化逻辑函数，以及如何仅使用多路复用器合成逻辑函数。如果你想把它当作纯粹的Verilog练习，你可以忽略这个约束，按照你自己的意愿编写模块。))
CORRECT1:
module top_module (
input c,
input d,
output [3:0] mux_in
);
always @(*) begin
case({c,d})
2'b0:
mux_in = 4'b0100; //当cd为00时，输出只与a有关系，因此当mux_in[2]=1时有输出；
2'b1:
mux_in = 4'b0001; //当cd为11时，输出与a'b'和ab有关系，因此当mux_in[0]=1并且mux_in[3]时有输出；
2'b11:
mux_in = 4'b1001;
default:
mux_in = 4'b0101;
endcase
end
endmodule
CORRECT2: //先确定ab,再谈论cd
module top_module (
input c,
input d,
output [3:0] mux_in
);
// After splitting the truth table into four columns,
// the rest of this question involves implementing logic functions
// using only multiplexers (no other gates).
// I will use the conditional operator for each 2-to-1 mux: (s ? a : b)
assign mux_in[0] = c ? 1 : d; // 1 mux: c|d
assign mux_in[1] = 0; // No muxes: 0
assign mux_in[2] = d ? 0 : 1; // 1 mux: ~d
assign mux_in[3] = c ? d : 0; // 1 mux: c&d
endmodule
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