错误代码
module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
reg [3:0]sslow,sshigh,mmlow,mmhigh,hhlow,hhhigh;
always@(posedge clk)
begin
if(reset)
begin
hhhigh<=4'd1;
hhlow <= 4'd2;
mmhigh<=0;
mmlow<=0;
sshigh<=0;
sslow<=0;
pm <= 0;
end
else if(ena && sslow<4'b1001)
begin
sslow <= sslow+'b1;
pm<=0;
end
else if(ena && sslow==4'b1001 && sshigh<4'd5)
begin
sslow<=0;
sshigh<=sshigh+'b1;
pm<=0;
end
else if(ena && sslow==4'b1001 && sshigh==4'd5 && mmlow<4'd9)
begin
sshigh<=0;
sslow<=0;
mmlow <= mmlow+'b1;
pm<=0;
end
else if(ena && sslow==4'b1001 && sshigh==4'd5 && mmlow==4'd9 && mmhigh<4'd5)
begin
sshigh<=0;
sslow<=0;
mmlow <= 0;
mmhigh <= mmhigh +'b1;
pm<=0;
end
else if(ena && sslow==4'b1001 && sshigh==4'd5 && mmlow==4'd9 && mmhigh==4'd5&&hhlow<4'd9)
begin
hhlow <= hhlow+'b1;
sshigh<=0;
mmhigh<=0;
mmlow <=0;
sslow<=0;
pm<=0;
end
else if(ena && sslow==4'b1001 && sshigh==4'd5 && mmlow==4'd9 && mmhigh==4'd5&&hhlow==4'd9&&hhhigh!=4'b1)
begin
sshigh<=0;
sslow<=0;
mmhigh<=0;
mmlow<=0;
hhlow<=0;
hhhigh <= 4'b1;
pm<=0;
end
else if(ena && sslow==4'b1001 && sshigh==4'd5 && mmlow==4'd9 && mmhigh==4'd5&&hhlow<4'd2&&hhhigh==4'd1)
begin
sshigh<=0;
sslow<=0;
mmhigh<=0;
mmlow<=0;
hhlow <=hhlow+1'b1;
pm<=0;
end
else if(ena && sslow==4'b1001 && sshigh==4'd5 && mmlow==4'd9 && mmhigh==4'd5&&hhlow==4'd1&&hhhigh==4'd1)
begin
sshigh<=0;
sslow<=0;
mmhigh<=0;
mmlow<=0;
hhlow <= 4'b1;
hhhigh <= 4'd2;
pm<=1;
end
else if(ena && sslow==4'b1001 && sshigh==4'd5 && mmlow==4'd9 && mmhigh==4'd5&&hhlow==4'd2&&hhhigh==4'd1)
begin
sshigh<=0;
sslow<=0;
mmhigh<=0;
mmlow<=0;
hhlow <= 4'b1;
hhhigh <= 4'd0;
pm<=0;
end
else
begin
sshigh<=sshigh;
sslow <=sslow;
mmhigh<=mmhigh;
mmlow<=mmlow;
hhhigh<=hhhigh;
hhlow<=hhlow;
end
end
assign ss[7:4]=sshigh;
assign ss[3:0] =sslow;
assign mm[7:4]=mmhigh;
assign mm[3:0] =mmlow;
assign hh[7:4]=hhhigh;
assign hh[3:0] =hhlow;
endmodule
结果:
module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
reg [3:0]sshigh,sslow,hhhigh,hhlow,mmhigh,mmlow;
always@(posedge clk)
begin
if(reset)
begin
sshigh<=0;
sslow<=0;
mmhigh<=0;
mmlow<=0;
hhhigh<=4'd1;
hhlow<=4'd2;
pm<=0;
end
else if(!ena)
begin
sshigh<=sshigh;
sslow<=sslow;
mmhigh<=mmhigh;
mmlow<=mmlow;
hhhigh<=hhhigh;
hhlow<=hhlow;
pm<=pm;
end
else if(sslow<4'd9)
begin
sslow <= sslow+'b1;
pm<=0;
end
else if(sslow==4'd9&&sshigh<4'd5)
begin
sslow<=0;
sshigh<=sshigh+'b1;
pm<=0;
end
else if(mmlow<4'd9&&sshigh == 4'd5&&sslow==4'd9)
begin
sshigh<=0;
sslow<=0;
mmlow <= mmlow+'b1;
pm<=0;
end
else if(mmhigh<4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
mmlow<=0;
sshigh<=0;
sslow<=0;
mmhigh<=mmhigh+'b1;
pm<=0;
end
else if(hhlow<4'd9&mmhigh==4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
hhlow<=hhlow+'b1;
mmhigh<=0;
mmlow<=0;
sshigh<=0;
sslow<=0;
pm<=0;
end
else if(hhlow==4'd9&&mmhigh==4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
hhhigh<=hhhigh+1'b1;
hhlow<=0;
mmhigh<=0;
mmlow<=0;
sshigh<=0;
sslow<=0;
pm<=0;
end
else if(!pm&&hhhigh==4'd1&&hhlow==4'd1&&mmhigh==4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
hhlow<=hhlow+'b1;
mmhigh<=0;
mmlow<=0;
sshigh<=0;
sslow<=0;
pm<=1;
end
else if(hhhigh==4'd1&&hhlow==4'd2&&mmhigh==4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
hhhigh<=0;
hhlow<=4'b1;
mmlow<=0;
mmhigh<=0;
sslow<=0;
sshigh<=0;
pm<=0;
end
end
assign ss={sshigh,sslow};
assign mm = {mmhigh,mmlow};
assign hh ={hhhigh,hhlow};
endmodule
修改后mm和ss没有错,其他的仍有错。
试试多个always块?不用 else if 语句?多个 always块中if语句 避免else if的逻辑? 猜测前面几题没做出来的计数器都是因为 else if语句和多个if语句的区别没搞清楚。
修改后,用if语句:
module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
reg [3:0]sshigh,sslow,hhhigh,hhlow,mmhigh,mmlow;
always@(posedge clk)
begin
if(reset)
begin
sshigh<=0;
sslow<=0;
mmhigh<=0;
mmlow<=0;
hhhigh<=4'd1;
hhlow<=4'd2;
pm<=0;
end
else if(!ena)
begin
sshigh<=sshigh;
sslow<=sslow;
mmhigh<=mmhigh;
mmlow<=mmlow;
hhhigh<=hhhigh;
hhlow<=hhlow;
pm<=pm;
end
else
begin
if(sslow<4'd9)
begin
sslow <= sslow+'b1;
pm<=0;
end
if(sslow==4'd9&&sshigh<4'd5)
begin
sslow<=0;
sshigh<=sshigh+'b1;
pm<=0;
end
if(mmlow<4'd9&&sshigh == 4'd5&&sslow==4'd9)
begin
sshigh<=0;
sslow<=0;
mmlow <= mmlow+'b1;
pm<=0;
end
if(mmhigh<4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
mmlow<=0;
sshigh<=0;
sslow<=0;
mmhigh<=mmhigh+'b1;
pm<=0;
end
if(hhlow<4'd9&mmhigh==4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
hhlow<=hhlow+'b1;
mmhigh<=0;
mmlow<=0;
sshigh<=0;
sslow<=0;
pm<=0;
end
if(hhlow==4'd9&&mmhigh==4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
hhhigh<=hhhigh+1'b1;
hhlow<=0;
mmhigh<=0;
mmlow<=0;
sshigh<=0;
sslow<=0;
pm<=0;
end
if(!pm&&hhhigh==4'd1&&hhlow==4'd1&&mmhigh==4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
hhlow<=hhlow+'b1;
mmhigh<=0;
mmlow<=0;
sshigh<=0;
sslow<=0;
pm<=1;
#(clk) pm<=0;
end
if(hhhigh==4'd1&&hhlow==4'd2&&mmhigh==4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
hhhigh<=0;
hhlow<=4'b1;
mmlow<=0;
mmhigh<=0;
sslow<=0;
sshigh<=0;
pm<=0;
end
end
end
assign ss={sshigh,sslow};
assign mm = {mmhigh,mmlow};
assign hh ={hhhigh,hhlow};
endmodule
结果:
修改:pm<=~pm;
module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
reg [3:0]sshigh,sslow,hhhigh,hhlow,mmhigh,mmlow;
always@(posedge clk)
begin
if(reset)
begin
sshigh<=0;
sslow<=0;
mmhigh<=0;
mmlow<=0;
hhhigh<=4'd1;
hhlow<=4'd2;
pm<=0;
end
else if(!ena)
begin
sshigh<=sshigh;
sslow<=sslow;
mmhigh<=mmhigh;
mmlow<=mmlow;
hhhigh<=hhhigh;
hhlow<=hhlow;
pm<=pm;
end
else
begin
if(sslow<4'd9)
begin
sslow <= sslow+'b1;
end
if(sslow==4'd9&&sshigh<4'd5)
begin
sslow<=0;
sshigh<=sshigh+'b1;
end
if(mmlow<4'd9&&sshigh == 4'd5&&sslow==4'd9)
begin
sshigh<=0;
sslow<=0;
mmlow <= mmlow+'b1;
end
if(mmhigh<4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
mmlow<=0;
sshigh<=0;
sslow<=0;
mmhigh<=mmhigh+'b1;
end
if(hhlow<4'd9&mmhigh==4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
hhlow<=hhlow+'b1;
mmhigh<=0;
mmlow<=0;
sshigh<=0;
sslow<=0;
end
if(hhlow==4'd9&&mmhigh==4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
hhhigh<=hhhigh+1'b1;
hhlow<=0;
mmhigh<=0;
mmlow<=0;
sshigh<=0;
sslow<=0;
end
if(!pm&&hhhigh==4'd1&&hhlow==4'd1&&mmhigh==4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
hhlow<=hhlow+'b1;
mmhigh<=0;
mmlow<=0;
sshigh<=0;
sslow<=0;
pm<=~pm;
end
if(hhhigh==4'd1&&hhlow==4'd2&&mmhigh==4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
hhhigh<=0;
hhlow<=4'b1;
mmlow<=0;
mmhigh<=0;
sslow<=0;
sshigh<=0;
end
end
end
assign ss={sshigh,sslow};
assign mm = {mmhigh,mmlow};
assign hh ={hhhigh,hhlow};
endmodule
修改: pm<=~pm 前的条件修改 把!pm删掉。结果成果。
module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
reg [3:0]sshigh,sslow,hhhigh,hhlow,mmhigh,mmlow;
always@(posedge clk)
begin
if(reset)
begin
sshigh<=0;
sslow<=0;
mmhigh<=0;
mmlow<=0;
hhhigh<=4'd1;
hhlow<=4'd2;
end
else if(!ena)
begin
sshigh<=sshigh;
sslow<=sslow;
mmhigh<=mmhigh;
mmlow<=mmlow;
hhhigh<=hhhigh;
hhlow<=hhlow;
end
else
begin
if(sslow<4'd9)
begin
sslow <= sslow+'b1;
end
if(sslow==4'd9&&sshigh<4'd5)
begin
sslow<=0;
sshigh<=sshigh+'b1;
end
if(mmlow<4'd9&&sshigh == 4'd5&&sslow==4'd9)
begin
sshigh<=0;
sslow<=0;
mmlow <= mmlow+'b1;
end
if(mmhigh<4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
mmlow<=0;
sshigh<=0;
sslow<=0;
mmhigh<=mmhigh+'b1;
end
if(hhlow<4'd9&mmhigh==4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
hhlow<=hhlow+'b1;
mmhigh<=0;
mmlow<=0;
sshigh<=0;
sslow<=0;
end
if(hhlow==4'd9&&mmhigh==4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
hhhigh<=hhhigh+1'b1;
hhlow<=0;
mmhigh<=0;
mmlow<=0;
sshigh<=0;
sslow<=0;
end
if(hhhigh==4'd1&&hhlow==4'd1&&mmhigh==4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
hhlow<=hhlow+'b1;
mmhigh<=0;
mmlow<=0;
sshigh<=0;
sslow<=0;
pm<=~pm;
end
if(hhhigh==4'd1&&hhlow==4'd2&&mmhigh==4'd5&&mmlow==4'd9&&sshigh==4'd5&&sslow==4'd9)
begin
hhhigh<=0;
hhlow<=4'b1;
mmlow<=0;
mmhigh<=0;
sslow<=0;
sshigh<=0;
end
end
end
assign ss={sshigh,sslow};
assign mm = {mmhigh,mmlow};
assign hh ={hhhigh,hhlow};
endmodule