Combinational Logic
Basic Gates
module top_module (
input in ,
output out) ;
assign out = in ;
endmodule
module top_module (
output out) ;
assign out = 0 ;
endmodule
module top_module (
input in1,
input in2,
output out) ;
assign out = ~ ( in1 | in2) ;
endmodule
module top_module (
input in1,
input in2,
output out) ;
assign out = in1 & ~ in2;
endmodule
module top_module (
input in1,
input in2,
input in3,
output out) ;
wire in1_in2 = in1 ^ in2;
assign out = in3 ^ ~ in1_in2;
endmodule
module top_module (
input a, b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
) ;
assign out_and = a & b;
assign out_or = a | b;
assign out_xor = a ^ b;
assign out_nand = ~ ( a & b) ;
assign out_nor = ~ ( a | b) ;
assign out_xnor = ~ ( a ^ b) ;
assign out_anotb = a & ~ b;
endmodule
module top_module (
input p1a, p1b, p1c, p1d,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y ) ;
assign p1y = ~ ( ( p1a & p1b) & ( p1c & p1d) ) ;
assign p2y = ~ ( ( p2a & p2b) & ( p2c & p2d) ) ;
endmodule
module top_module (
input x3,
input x2,
input x1,
output f
) ;
assign f = ( ~ x3 & x2) | ( x3 & x1) ;
endmodule
module top_module ( input [ 1 : 0 ] A, input [ 1 : 0 ] B, output z ) ;
assign z = ~ ( | ( A ^ B) ) ;
endmodule
module top_module ( input x, input y, output z) ;
assign z = ( x ^ y) & x;
endmodule
module top_module ( input x, input y, output z ) ;
assign z = ~ ( x ^ y) ;
endmodule
Combine Circuits A and B 题目链接
module top_module ( input x, input y, output z) ;
wire A_out = x & ~ y;
wire B_out = ~ ( x ^ y) ;
assign z = ( A_out | B_out) ^ ( A_out & B_out) ;
endmodule
module top_module (
input ring,
input vibrate_mode,
output ringer,
output motor
) ;
assign { ringer, motor} = ring ? ( vibrate_mode ? 2 'b01 : 2' b10) : 2 'b00;
endmodule
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
) ;
assign heater = ( mode & too_cold) ;
assign aircon = ( ~ mode & too_hot) ;
assign fan = fan_on | ( heater | aircon) ;
endmodule
3-bit population count 题目链接
module top_module (
input [ 2 : 0 ] in ,
output [ 1 : 0 ] out ) ;
assign out[ 1 ] = ( in [ 1 ] & in [ 0 ] ) | ( in [ 2 ] & in [ 1 ] ) | ( in [ 2 ] & in [ 0 ] ) ;
assign out[ 0 ] = ( in [ 2 ] ^ in [ 1 ] ^ in [ 0 ] ) ;
endmodule
module top_module (
input [ 3 : 0 ] in ,
output [ 2 : 0 ] out_both,
output [ 3 : 1 ] out_any,
output [ 3 : 0 ] out_different ) ;
assign out_both[ 2 : 0 ] = { in [ 3 ] & in [ 2 ] , in [ 2 ] & in [ 1 ] , in [ 1 ] & in [ 0 ] } ;
assign out_any[ 3 : 1 ] = { in [ 3 ] | in [ 2 ] , in [ 2 ] | in [ 1 ] , in [ 1 ] | in [ 0 ] } ;
assign out_different[ 3 : 0 ] = { in [ 0 ] ^ in [ 3 ] , in [ 3 ] ^ in [ 2 ] , in [ 2 ] ^ in [ 1 ] , in [ 1 ] ^ in [ 0 ] } ;
endmodule
module top_module (
input [ 99 : 0 ] in ,
output [ 98 : 0 ] out_both,
output [ 99 : 1 ] out_any,
output [ 99 : 0 ] out_different ) ;
assign out_both[ 98 : 0 ] = in [ 99 : 1 ] & in [ 98 : 0 ] ;
assign out_any[ 99 : 1 ] = in [ 99 : 1 ] | in [ 98 : 0 ] ;
assign out_different[ 99 : 0 ] = { in [ 0 ] , in [ 99 : 1 ] } ^ in [ 99 : 0 ] ;
endmodule
Multiplexers
module top_module (
input a, b, sel,
output out ) ;
assign out = sel ? b : a;
endmodule
2-to-1 bus multiplexer 题目链接
module top_module (
input [ 99 : 0 ] a, b,
input sel,
output [ 99 : 0 ] out ) ;
assign out = sel ? b : a;
endmodule
module top_module (
input [ 15 : 0 ] a, b, c, d, e, f, g, h, i,
input [ 3 : 0 ] sel,
output [ 15 : 0 ] out ) ;
reg [ 15 : 0 ] out_reg;
assign out = out_reg;
always @ ( * ) begin
case ( sel)
0 : out_reg = a;
1 : out_reg = b;
2 : out_reg = c;
3 : out_reg = d;
4 : out_reg = e;
5 : out_reg = f;
6 : out_reg = g;
7 : out_reg = h;
8 : out_reg = i;
default: out_reg = { 16 { 1 'b1} } ;
endcase
end
endmodule
256-to-1 multiplexer 题目链接
module top_module (
input [ 255 : 0 ] in ,
input [ 7 : 0 ] sel,
output out ) ;
assign out = in [ sel] ;
endmodule
256-to-1 4-bit multiplexer 题目链接
module top_module (
input [ 1023 : 0 ] in ,
input [ 7 : 0 ] sel,
output [ 3 : 0 ] out ) ;
assign out = { in [ 4 * sel + 3 ] , in [ 4 * sel + 2 ] , in [ 4 * sel + 1 ] , in [ 4 * sel] } ;
endmodule
Arithmetic Circuits
module top_module (
input a, b,
output cout, sum ) ;
assign cout = a & b;
assign sum = a ^ b;
endmodule
module top_module (
input a, b, cin,
output cout, sum ) ;
assign sum = a ^ b ^ cin;
assign cout = ( a & b) | ( a & cin) | ( b & cin) ;
endmodule
module top_module (
input [ 2 : 0 ] a, b,
input cin,
output [ 2 : 0 ] cout,
output [ 2 : 0 ] sum ) ;
genvar i;
generate
for ( i = 0 ; i < 3 ; i = i + 1 ) begin : faddr_for
if ( i == 0 ) begin : faddr_for_0
assign sum[ i] = a[ i] ^ b[ i] ^ cin;
assign cout[ i] = ( a[ i] & b[ i] ) | ( a[ i] & cin) | ( b[ i] & cin) ;
end
else begin : faddr_for_else
assign sum[ i] = a[ i] ^ b[ i] ^ cout[ i - 1 ] ;
assign cout[ i] = ( a[ i] & b[ i] ) | ( a[ i] & cout[ i - 1 ] ) | ( b[ i] & cout[ i - 1 ] ) ;
end
end
endgenerate
endmodule
module top_module (
input [ 3 : 0 ] x,
input [ 3 : 0 ] y,
output [ 4 : 0 ] sum) ;
wire [ 3 : 0 ] cout;
genvar i;
assign sum[ 4 ] = cout[ 3 ] ;
generate
for ( i = 0 ; i < 4 ; i = i + 1 ) begin : generate_fadd_for
if ( i == 0 ) begin : fadd_0
assign sum[ i] = x[ i] ^ y[ i] ;
assign cout[ i] = x[ i] & y[ i] ;
end
else begin : fadd_else
assign sum[ i] = x[ i] ^ y[ i] ^ cout[ i - 1 ] ;
assign cout[ i] = ( x[ i] & y[ i] ) | ( x[ i] & cout[ i - 1 ] ) | ( cout[ i - 1 ] & y[ i] ) ;
end
end
endgenerate
endmodule
Signed addition overflow 题目链接
module top_module (
input [ 7 : 0 ] a,
input [ 7 : 0 ] b,
output [ 7 : 0 ] s,
output overflow
) ;
assign s = { a + b} ;
assign overflow = ( ~ a[ 7 ] & ~ b[ 7 ] & s[ 7 ] ) | ( a[ 7 ] & b[ 7 ] & ~ s[ 7 ] ) ;
endmodule
100-bit binary adder 题目链接
module top_module (
input [ 99 : 0 ] a, b,
input cin,
output cout,
output [ 99 : 0 ] sum ) ;
assign { cout, sum} = ( a + b + cin) ;
endmodule
module top_module (
input [ 15 : 0 ] a, b,
input cin,
output cout,
output [ 15 : 0 ] sum ) ;
wire [ 2 : 0 ] cout_tmp;
wire [ 3 : 0 ] cin_wire;
assign cin_wire = { cout_tmp, cin} ;
wire [ 3 : 0 ] cout_wire;
assign { cout, cout_tmp} = cout_wire;
genvar i;
generate
for ( i = 0 ; i < 4 ; i = i + 1 ) begin : generate_bcd_fadd_for
bcd_fadd bcd_fadd_inst (
. a ( a[ 4 * i + 3 : 4 * i] ) ,
. b ( b[ 4 * i + 3 : 4 * i] ) ,
. cin ( cin_wire[ i] ) ,
. cout ( cout_wire[ i] ) ,
. sum ( sum[ 4 * i + 3 : 4 * i] ) ) ;
end
endgenerate
endmodule
Karnaugh Map to Circuit
module top_module (
input a,
input b,
input c,
output out ) ;
assign out = a | b | c;
endmodule
module top_module (
input a,
input b,
input c,
input d,
output out ) ;
reg out_reg;
assign out = out_reg;
always @ ( * ) begin
case ( { a, b, c, d} )
'b1100: out_reg = 0 ;
'b1101: out_reg = 0 ;
'b0101: out_reg = 0 ;
'b0011: out_reg = 0 ;
'b1110: out_reg = 0 ;
'b1010: out_reg = 0 ;
default: out_reg = 1 ;
endcase
end
endmodule
module top_module (
input a,
input b,
input c,
input d,
output out ) ;
assign out = a | ( ~ b & c) ;
endmodule
module top_module (
input a,
input b,
input c,
input d,
output out ) ;
assign out = a ^ b ^ c ^ d;
endmodule
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
) ;
assign out_sop = ( c & d) | ( ~ a & ~ b & c) ;
assign out_pos = c & ( ~ a | b) & ( ~ c | d | ~ b) ;
endmodule
module top_module (
input [ 4 : 1 ] x,
output f ) ;
assign f = ( x[ 1 ] | x[ 3 ] ) & ( ~ x[ 1 ] | ~ x[ 3 ] ) & ( x[ 2 ] | x[ 3 ] ) ;
endmodule
module top_module (
input [ 4 : 1 ] x,
output f
) ;
assign f = ( ~ x[ 2 ] & ~ x[ 4 ] ) | ( ~ x[ 1 ] & x[ 3 ] ) | ( x[ 2 ] & x[ 3 ] & x[ 4 ] ) ;
endmodule
K-map implemented with a multiplexer 题目链接
module top_module (
input c,
input d,
output [ 3 : 0 ] mux_in
) ;
assign mux_in = { c & d, ~ d, 1 'b0, c | d} ;
endmodule
* ### [题目链接]() ```clike s ```