呼吸灯的Verilog设计

Verilog代码

module led_breathing(
    input clk,      							//50M
    input rst_n,
    output led);

    reg [15:0] i;                        		//亮灯时间
    reg [15:0] cnt_led;                	//计时器
    reg        flag = 0;
    localparam        T=50_000;     //1ms  
    
    always@(posedge clk or negedge rst_n)begin 
        if(!rst_n)begin
            cnt_led <=0;
            flag    <=0;
            i       <=0;
        end
        else if(cnt_led==T-1) begin 
            cnt_led <= 0;
            if(!flag) begin
                if(i==T) flag <= 1;
                else i <= i+50;
             end
             else begin
                if(i==0) flag <= 0;
                else i <= i-50;
             end
        end
        else cnt_led <= cnt_led+1;
    end
    assign led = cnt_led<i;
endmodule