HDLBits_Exams/review2015 fancytimer

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output [3:0] count,
    output counting,
    output done,
    input ack );
    parameter S0=0,S1=1,S2=2,S3=3,B0=4,B1=5,B2=6,B3=7,cnt=8,waiting=9;
    reg [3:0] cs,ns;
    reg [9:0] q;
    
    always @(*)
        begin
            case (cs)
                S0:ns=data?S1:S0;
                S1:ns=data?S2:S0;
                S2:ns=data?S2:S3;
                S3:ns=data?B0:S0;
                B0:ns=B1;
                B1:ns=B2;
                B2:ns=B3;
                B3:ns=cnt;
                cnt:ns=count==4'b0&&q==10'd999 ? waiting:cnt;
                waiting:ns=ack ? S0:waiting;
            endcase
        end

    always @(posedge clk)
        begin
            if (reset)
                cs<=S0;
            else
                cs<=ns;
        end
    
    always @(posedge clk)
        begin
            if (reset)
                count<=4'd0;
            else if(cs==B0 || cs==B1 || cs==B2 || cs==B3)
                count<={count[2:0],data};
            else if(ns==cnt)begin
                if(q==10'd999)begin                    
                    if(count==4'b0)begin
                        count<=4'b0;
                    end
                    else
                        count<=count-1'b1;
                end
                else
                    count<=count;
            end
        end    

    always @ (posedge clk)
        begin
            if (reset | q==10'd999 | cs==B3)
                q<=0;
            else
                q<= q+1'b1;
        end

    assign counting=(cs==cnt);
    assign done = (cs==waiting);
    
endmodule