HDLBits Exams/ece241 2013 q4

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
); 
    parameter A=4'b0000,B=4'b0010,C=4'b0011,D=4'b0110,E=4'b0111,F=4'b1111;
    reg [3:1] p_s;
    reg [3:0] state,next_state;
    
    always@(*)begin
    case(s)
        3'b111: next_state = A;
        3'b011: next_state = p_s>s ? C:(p_s==s ? {3'b001,state[0]} : B);
        3'b001: next_state = p_s>s ? E:(p_s==s ? {3'b011,state[0]} : D);
        3'b000: next_state = F;
    endcase
    end
    
    always@(posedge clk)begin
        if(reset)begin
            state<=F;
            p_s<=3'b000;
        end
        else begin
            state<=next_state;
        	p_s<=s;
        end
    end
    
    assign {fr3,fr2,fr1,dfr}=state;
   

endmodule