HDLBits_Fsm serialdp

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
    parameter data=0,idle=1,start=2,stop=3,waiting=4,parity=5;
    reg [3:0] count;
    reg [2:0] state,next_state;
    wire odd,reset_p;
    
    parity inst1(clk,reset_p,in,odd);
    
    always@(*)begin
        case (state)
            data:next_state = count>7 ? (in^odd ? parity:waiting):data;
            parity:next_state = in ? stop:waiting;
            idle:next_state = in ? idle:start;
            start:next_state = data;
            stop:next_state = in ? idle:start;
            waiting:next_state = in ? idle:waiting;
        endcase
    end
    
    always@(posedge clk)begin
        if(reset)
            state <= idle;
        else
            state <= next_state;
    end
    
    always@(posedge clk)begin
        if(next_state==data)begin
            count<=count + 4'd1;
            out_byte[count] <= in;
        end   
        else
            count<=4'd0;
    end

    assign reset_p = (next_state == start || reset == 1'b1);
    assign done = (state==stop);

endmodule

感觉写了一百遍