HDLBits__Fsm serial

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
    parameter data=0,idle=1,start=2,stop=3,waiting=4;
    reg [3:0] count;
    reg [2:0] state,next_state;
    
    always@(*)begin
        case (state)
            data:next_state = count>7 ? (in?stop:waiting):data;
            idle:next_state = in ? idle:start;
            start:next_state = data;
            stop:next_state = in ? idle:start;
            waiting:next_state = in ? idle:waiting;
        endcase
    end
    always@(posedge clk)begin
        if(reset)
            state <= idle;
        else
            state <= next_state;
    end
    always@(posedge clk)begin
        if(next_state==data)
            count<=count + 4'd1;
        else
            count<=4'd0;
    end
    assign done=(state==stop);
        

endmodule

费死劲了，状态转换还是不太熟练