module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
wire ena_m,ena_h;
always @(posedge clk) begin
if(reset)
pm<=1'b0;
else begin
if(ss[7:0]==8'h58)
ena_m<=1'b1;
else
ena_m<=1'b0;
if(mm[7:0]==8'h59 && ss[7:0]==8'h58)
ena_h<=1'b1;
else
ena_h<=1'b0;
if(mm[7:0]==8'h59 && ss[7:0]==8'h59 && hh[7:0]==8'h11)begin
if(pm==1'b1)
pm<=1'b0;
else
pm<=1'b1;
end
end
end
decade_cnt inst1(clk,reset,ena,ss[7:0]);
decade_cnt inst2(clk,reset,ena_m,mm[7:0]);
hour insth(clk,reset,ena_h,hh[7:0]);
endmodule
module decade_cnt (
input clk,
input reset,
input enable,
output [7:0] q
);
always @(posedge clk) begin
if (reset)
q <= 8'h00;
else if (enable) begin
if (q==8'h59)
q <= 8'h00;
else if(q[3:0]==4'h9) begin
q[7:4]<=q[7:4]+1'h1;
q[3:0]<=4'h0;
end
else begin
q[7:4]<=q[7:4];
q[3:0]<=q[3:0]+1'h1;
end
end
else
q <= q;
end
endmodule
module hour(
input clk,
input reset,
input enable,
output [7:0] q
);
always @(posedge clk) begin
if (reset)
q <= 8'h12;
else if (enable) begin
if (q==8'h12)
q <= 8'h01;
else if(q[3:0]==4'h9) begin
q[7:4]<=q[7:4]+1'h1;
q[3:0]<=4'h0;
end
else begin
q[7:4]<=q[7:4];
q[3:0]<=q[3:0]+1'h1;
end
end
else
q <= q;
end
endmodule
终于能自己获得一个success了,不容易,贴出来记录一下。