时序逻辑的测试模板

时序逻辑的测试模块
代码：
module p2s(data_in,clock,reset,load,data_out,done);
input [3:0] data_in;
input clock,reset,load;
output data_out;
output done;
reg done;

reg [3:0] temp;
reg [3:0] cnt;

always@(posedge clock or posedge reset )
begin
if(reset)
begin
temp<=0;
cnt<=0;
done<=1;
end
else if(load)
begin
temp<=data_in;
cnt<=0;
done<=0;
end
else if(cnt==3)
begin
temp <= {temp[2:0],1’b0};
cnt<=0;
done<=1;
end
else
begin
temp <= {temp[2:0],1’b0};
cnt<=cnt+1;
done<=0;
end
end

assign data_out=(done==1)?1’bz:temp[3];

endmodule

module tbp2s;
reg [3:0] data_in;
reg clock,reset,load;
wire data_out;
wire done;

initi