2021-06-21

优先级编码器的Verilog设计

1.建立文件priority，并编写代码
代码:
module priority(W,Y,z);
input [3:0]W;
output reg [1:0]Y;
output reg z;

always @(W)
begin
z=1;
casex(W)
4’b1xxx:Y=3;
4’b01xx:Y=2;
4’b001X:Y=1;
4’b0001:Y=0;
default: begin
z=0;
Y=2’bx;
end
endcase
end

endmodule

2.保存，点击compile，检查是否出错，检查结果如下
3.点击work，编译文件，如图:
4.将sim中的测试代码加入到wave

5.点击run,开始测试,测试结果如图


视频链接:https://v.qq.com/x/page/m3254vn9kru.html

Verilog HDL高级数学设计(第二版)p80 例4.8

1.新建三个文件
(1)Add_full_unit_delay
(2)Add_half_unit_delay
(3)tb_Add_full_unit_delay

2.分别编写代码
代码
(1)
module Add_full_unit_delay(output c_out,sum,input a,b,c_in);
wire w1,w2,w3;
Add_half_unit_delay M1(w2,w1,a,b);
Add_half_unit_delay M2(w3,sum,w1,c_in);
or #1 M3(c_out,w2,w3);
endmodule
(2)
module Add_half_unit_delay (output c_out,sum,input a,b);
xor #1 M1(sum,a,b);
and #1 M2(c_out,a,b);
endmodule
(3)
module tb_Add_full_unit_delay();
reg a, b, c_in;
wire sum, c_out;

Add_full_unit_delay fulladd(.c_out(c_out),.sum(sum),.a(a),.b(b),.c_in(c_in));

initial
begin
a=1’b0;b=1’b0;c_in=1’b0;
#5 a=1’b0;b=1’b0;c_in=1’b0;
#5 a=1’b0;b=1’b1;c_in=1’b0;
#5 a=1’b1;b=1’b1;c_in=1’b0;
#5 a=1’b1;b=1’b0;c_in=1’b0;
#5 a=1’b0;b=1’b0;c_in=1’b1;
#5 a=1’b0;b=1’b1;c_in=1’b1;
#5 a=1’b1;b=1’b1;c_in=1’b1;
#5 a=1’b1;b=1’b0;c_in=1’b1;
#20 $stop;
end

endmodule

3.点击compile all,检查是否出错

4.在work中点击测试文件 tb_Add_full_unit_delay

5.点击Add wave 添加波形图

6.点击run all 出现波形图

视频链接:https://v.qq.com/x/page/e3255uiajw9.html

篮球计时器

1.新建两个文件夹
(1)digital
(2)tbdigital

2.编写代码
(1)module digital(TimerH,TimerL,over,Reset,Stop,clk);
output [6:0]TimerH;
output [6:0]TimerL;
output over;
input Reset;
input Stop;
input clk;
wire [1:0]H;
wire [3:0]L;
wire clk_1;
fenpin UO (.clk(clk),.clk_old(clk_1));
basketballtimer U1(over, H[1:0],L[3:0], Reset, Stop,clk_1);
CD4511 U2 (TimerH[6:0], {2’b00,H[1:0]});
CD4511 U3 (TimerL[6:0], L[3:0]);
endmodule

module fenpin (clk_old, clk);
output clk_old;
input clk;
reg[24:0] count;
reg clk_old;
always @(posedge clk)
begin
if(count==25’b1_1001_0000_0000_0000_0000_0000)
begin
clk_old<=~clk_old;
count<=0;
end
else
count<=count+1;
end

endmodule

module basketballtimer (Over,TimerH, TimerL,Reset,Stop,clk_1);
output Over;
output [1:0]TimerH;
output [3:0]TimerL;
input Reset;
input Stop;
input clk_1;

reg [4:0] Q;

assign Over =(Q== 5 'd0);
assign TimerH=Q/10;
assign TimerL=Q%10;

always @(posedge clk_1 or negedge Reset or negedge Stop)
begin
if(~Reset)
Q <= 5’d23;
else
begin
if(~Stop)
Q <= Q;
else
begin
if(Q>5’d0)
Q <= Q - 1’b1;
else
Q <=Q;
end
end
end
endmodule

module CD4511 (Y,A);
output reg [6:0]Y;
input [3:0]A;
always @(*)
begin
case(A)
4’d0: Y<=7’b1000_000;
4 'd1: Y<=7’b1111_001;
4 'd2: Y<=7’b0100_100;
4’d3: Y<=7’b0110_000;
4 'd4:Y<=7’b0011_001;
4 'd5: Y<=7’b0010_010;
4 'd6: Y<=7’b0000_010;
4 'd7: Y<=7’b1111_000;
4 'd8: Y<=7 'b0000_000;
4’d9: Y<=7’b0010_000;
default: Y<=7’b1000_000;
endcase
end
endmodule

(2)
module tbdigital;
wire [6:0]TimerH;
wire [6:0]TimerL;
wire over;
reg Reset;
reg Stop;
reg clk;
initial
begin
clk=0;
Reset=1;
Stop=1;
#10 Reset=0;
#20 Reset=1;
#200 Stop=0;
#50 Stop=1;
@ (posedge over);
#10 $stop;
end

always #5 clk=~clk;
digital idigital (TimerH, TimerL, over,Reset, Stop, clk);
endmodule

3.点击compile all ,检查是否出错

4.在work中点击测试文件tbdigital
5.点击Add wave添加波形图

6.点击run all 出现波形图

视频链接:https://v.qq.com/x/page/a3255yeaisj.html